A digital-to-analog converter circuit generates an analog transmitted signal according to a digital transmitted signal. A first echo canceller circuit generates a first echo cancelling signal according to the digital transmitted signal. A processor circuit generates an analog processed signal according to the analog transmitted signal, the first echo cancelling signal, and a received signal. An analog-to-digital converter circuit generates a digital value according to the analog processed signal and two slicer levels of a plurality of slicer levels. A storage circuit stores a look-up table. The look-up table records an offset value corresponding to the digital value. The storage circuit further outputs a first output signal according to the digital value and the offset value. The offset value is updated according to an error value associated with the first output signal.

A time-interleaved analog to digital converter includes capacitor array circuits, at least one successive approximation register circuitry, and at least one noise shaping circuitry. The capacitor array circuits are configured to alternately sample an input signal, in order to generate a sampled input signal. The at least one successive approximation register circuitry is configured to perform an analog to digital conversion according to the sampled input signal and a residue signal, in order to generate at least one digital output. The at least one noise shaping circuitry is configured to utilize at least one first circuit in switched-capacitor circuits to transfer the residue signal from a first capacitor array circuit in the capacitor array circuits, and randomly select at least one second circuit from the switched-capacitor circuits to cooperate with a second capacitor array circuit in the capacitor array circuits to sample the input signal.

A high resolution analog to digital converter (ADC) with improved bandwidth senses an analog signal (e.g., a load current) to generate a digital signal. The ADC operates based on a load voltage produced based on charging of an element (e.g., a capacitor) by a load current and a digital to analog converter (DAC) output current (e.g., from a N-bit DAC). The ADC generates a digital output signal representative of a difference between the load voltage and a reference voltage. This digital output signal is used directly, or after digital signal processing, to operate an N-bit DAC to generate a DAC output current that tracks the load current. In addition, quantization noise is subtracted from the digital output signal thereby extending the operational bandwidth of the ADC. In certain examples, the operational bandwidth of the ADC extends up to 100s of kHz (e.g., 200-300 kHz), or even higher.

A noise-shaping enhanced (NSE) gated ring oscillator (GRO)-based ADC includes a delay which delays and feedbacks an error signal to an input of the NSE GRO-based ADC. The feedback error signal provides an order of noise-shaping and the error signal is generated at the input of the NSE GRO-based ADC from an input signal, the feedback error signal, and a front-end output. A voltage-to-time converter converts the error signal to the time domain. A GRO outputs phase signals from the time domain error signal by oscillating when the error signal is high and inhibiting oscillation otherwise. A quantization device quantizes the phase signals to generate the front-end output. A quantization extraction device determines a quantization error from the quantized phase signals. A time-to-digital converter digitizes the quantization error to generate a back-end output. An output device generates a second order noise-shaped output based on the front-end and the back-end outputs.

An analog-to-digital converter, ADC, circuitry, comprises: an integrator connected to a capacitor, the integrator being configured to switch between integrating an analog input signal for ramping an integrator output and integrating a reference input signal for returning integrator output towards a threshold; a comparator for comparing integrator output to the threshold; and a timer for determining a time duration during which the reference input signal is integrated, the time duration providing a digital representation of an analog input signal value; the ADC circuitry further comprising a feedforward noise shaping loop configured to store a quantization error signal based on digitizing a first sample, the comparator being configured to receive a feedforward noise shaping signal for changing the threshold for digitizing a later sample of the analog input signal following the first sample.

A high resolution analog to digital converter (ADC) with improved bandwidth senses an analog signal (e.g., a load current) to generate a digital signal. The ADC operates based on a load voltage produced based on charging of an element (e.g., a capacitor) by a load current and a digital to analog converter (DAC) output current (e.g., from a N-bit DAC). The ADC generates a digital output signal representative of a difference between the load voltage and a reference voltage. This digital output signal is used directly, or after digital signal processing, to operate an N-bit DAC to generate a DAC output current that tracks the load current. In addition, quantization noise is subtracted from the digital output signal thereby extending the operational bandwidth of the ADC. In certain examples, the operational bandwidth of the ADC extends up to 100s of kHz (e.g., 200-300 kHz), or even higher.

A signal processing apparatus includes a plurality of time-interleaving digital-to-analog converters each configured to sample a digital input signal at a preset sub-DAC sample frequency, and to generate an analog sub-DAC output signal. The signal processing apparatus includes analog multiplexer that samples the plurality of sub-DAC output signals at a preset multiplexer clock frequency and generates a multiplexer output signal. The signal processing apparatus further includes a local ADC that receives the multiplexer output signal and generate a digital feedback signal. The signal processing apparatus further includes a digital compensation engine that receives the digital feedback signal from the local ADC and determine one or more distortion compensation parameters. The signal processing apparatus further includes a digital pre-processing stage that receives the one or more distortion compensation parameters from the digital compensation engine and performs distortion compensation pre-processing on the digital input signal.

A kickback current is suppressed so as not to generate a deviation in a signal that outputs a comparison result.

A comparator includes a first input terminal and a second input terminal to which a first differential input signal pair is input, a third input terminal and a fourth input terminal to which a second differential input signal pair is input, a first comparison circuit that outputs a signal corresponding to a difference signal of the first differential input signal pair generated by connecting the first input terminal to a positive side and connecting the second input terminal to a negative side and a difference signal of the second differential input signal pair generated by connecting the third input terminal to a positive side and connecting the fourth input terminal to a negative side, and a second comparison circuit that outputs a signal corresponding to a difference signal of the first differential input signal pair generated by connecting the first input terminal to a negative side and connecting the second input terminal to a positive side, and a difference signal of the second differential input signal pair generated by connecting the third input terminal to a positive side and connecting the fourth input terminal to a negative side.

Systems and methods are provided for analog-to-digital conversion (ADC). A first quantization stage may be configured to receive an analog input signal and sample the analog input signal to generate a first digital signal, the first quantization stage may be further configured to filter the first digital signal with a first noise-shaping transfer function to generate a first noise-shaped digital output and to generate a quantization error signal based on a comparison of the analog input signal and the first noise-shaped digital output. A voltage controlled oscillator (VCO)-based second quantization stage may be configured to receive the quantization error signal and sample the quantization error signal to generate a second digital signal, the VCO-based second quantization stage may be further configured to filter the second digital signal with a second noise-shaping transfer function to generate a second noise-shaped digital output. A first digital filter may be configured to filter the first noise-shaped digital output with an equivalent signal transfer function of the VCO-based second quantization stage to generate a first stage digital output. A second digital filter may be configured to filter the second noise-shaped digital output with the first noise-shaping transfer function to generate a second stage digital output with second order noise-shaping characteristics A combination circuit may combine the first stage digital output and the second stage digital output to generate a digital ADC output signal with second order noise shaping characteristics.

A signal processing circuit for a gyroscope apparatus is disclosed. The signal processing circuit includes a first electrode and a second electrode pairing with the first electrode. The signal processing circuit, being a negative feedback loop circuit, is configured to be connected with the first electrode and the second electrode and comprises a demodulator configured to convert a current from the first electrode into a voltage and demodulate the converted voltage to output a demodulated signal, an analog-to-digital converter configured to convert the demodulated signal from the demodulator into a digital signal, a proportional-integral-derivative controller that is connected to the analog-to-digital converter, a digital-to-analog converter configured to convert an output signal from the proportional-integral-derivative controller to an analog signal, and a modulator configured to be electrically connected with the second electrode and to be electrically connected with the digital-to-analog converter.