A comparison control circuit is adapted to analog-to-digital converters and low-dropout regulators. The comparison control circuit includes a comparator, a Schmitt trigger, a capacitor set and a logic circuit. The comparator is configured to output a comparison signal according to a first input signal and a second input signal, wherein the comparison signal is a first high voltage potential or a first low voltage potential. The Schmitt trigger is configured to output a trigger signal according to the comparison signal and a voltage potential range, wherein the voltage potential range is in a range from the first low voltage potential to the first high voltage potential. The capacitor set is configured to adjust the second input signal when being controlled. The logic circuit is configured to control the capacitor set according to the trigger signal to correspondingly adjust the second input signal.

An Analog-to-Digital Converter (ADC) includes a plurality of ADC channels connected to an in-service signal input via an isolated power combiner; an on-chip circuit including a calibration source connected to the isolated power combiner; and one or more switches configured to switch the ADC between an in-service mode and a calibration mode. The one or more switches are set such that, in the calibration mode, the in-service signal input is disconnected and the on-chip circuit is connected to the isolated power combiner, and, in the in-service mode, the in-service signal input is connected and the on-chip circuit is disconnected to the isolated power combiner. In the calibration mode, the on-chip circuit is configured to provide a test signal to the plurality of ADC channels for a determination of interleave errors in the plurality of ADC channels.

An Analog-to-Digital Converter (ADC) includes a plurality of ADC channels connected to an in-service signal input via an isolated power combiner; an on-chip circuit including a calibration source connected to the isolated power combiner; and one or more switches configured to switch the ADC between an in-service mode and a calibration mode. The one or more switches are set such that, in the calibration mode, the in-service signal input is disconnected and the on-chip circuit is connected to the isolated power combiner, and, in the in-service mode, the in-service signal input is connected and the on-chip circuit is disconnected to the isolated power combiner. In the calibration mode, the on-chip circuit is configured to provide a test signal to the plurality of ADC channels for a determination of interleave errors in the plurality of ADC channels.

A Successive Approximation Register, SAR, Analog to Digital Converter, ADC, (50) achieves high speed and accuracy by (1) alternating at least some decisions between sets of comparators having different accuracy and noise characteristics, and (2) unevenly allocating redundancy (in the form of LSBs of range) for successive decisions according to the accuracy/noise of the comparator used for the preceding decision. The redundancy allocation is compensated by the addition of decision cycles. Alternating between different comparators removes the comparator reset time (treset) from the critical path, at least for those decision cycles. The uneven allocation of redundancy—specifically, allocating more redundancy to decision cycles immediately following the use of a lower accuracy/higher noise comparators—compensates for the lower accuracy and prevents the need for larger redundancy (relative to the full-scale range of a decision cycle) later in the ADC process.

A Successive Approximation Register, SAR, Analog to Digital Converter, ADC, (50) achieves high speed and accuracy by (1) alternating at least some decisions between sets of comparators having different accuracy and noise characteristics, and (2) unevenly allocating redundancy (in the form of LSBs of range) for successive decisions according to the accuracy/noise of the comparator used for the preceding decision. The redundancy allocation is compensated by the addition of decision cycles. Alternating between different comparators removes the comparator reset time (treset) from the critical path, at least for those decision cycles. The uneven allocation of redundancy—specifically, allocating more redundancy to decision cycles immediately following the use of a lower accuracy/higher noise comparators—compensates for the lower accuracy and prevents the need for larger redundancy (relative to the full-scale range of a decision cycle) later in the ADC process.

A high resolution analog to digital converter (ADC) with improved bandwidth senses an analog signal (e.g., a load current) to generate a digital signal. The ADC operates based on a load voltage produced based on charging of an element (e.g., a capacitor) by a load current and a digital to analog converter (DAC) output current (e.g., from a N-bit DAC). The ADC generates a digital output signal representative of a difference between the load voltage and a reference voltage. This digital output signal is used directly, or after digital signal processing, to operate an N-bit DAC to generate a DAC output current that tracks the load current. In addition, quantization noise is subtracted from the digital output signal thereby extending the operational bandwidth of the ADC. In certain examples, the operational bandwidth of the ADC extends up to 100s of kHz (e.g., 200-300 kHz), or even higher.

In a solid-state imaging element equipped with per-column ADCs, noise is reduced. A test signal source generates a test signal of a predetermined level. An analog-to-digital converter increases/decreases an analog signal according to an analog gain selected from among a plurality of analog gains, and converts the increased/decreased analog signal to a digital signal. An input switching section inputs, as the analog signal, either a test signal or a pixel signal to the analog-to-digital converter. A correction value calculation section obtains, on the basis of the test signal and the digital signal, a correction value for correcting an error in the selected analog gain, and outputs the correction value. A correction section corrects the digital signal according to the outputted correction value.

Aspects of the description provide for an analog-to-digital converter (ADC) operable to convert an analog input signal to an output signal at an output of the ADC. In some examples, the ADC includes multiple sub-ADCs coupled in parallel, each of the multiple sub-ADCs coupled to the output of the ADC and operable to receive the analog input signal. The ADC is configured to operate the sub-ADCs in a consecutive operation loop including a transition phase in which the ADC operates each of the sub-ADCs sequentially for a first number of sequences, an estimation phase in which the ADC operates each of the sub-ADCs sequentially for a second number of sequences following the first number of sequences, and a randomization phase in which the ADC operates subsets of the sub-ADCs for a third number of sequences following the second number of sequences.

A SAR ADC (50) is disclosed. It comprises a differential input port having a first input (V.sub.inP) configured to receive a first input voltage and a second input (V.sub.inN) configured to receive a second input voltage, of opposite polarity compared with first input voltage. Furthermore, it comprises a (300) having a first sub circuit (310P) comprising a first plurality of capacitors (2C.sub.u, C.sub.u), each connected to a common node (320P) of the first sub circuit (310P) with a first terminal, and a second sub circuit (310N) comprising a second plurality of capacitors (2C.sub.u, C.sub.u), each connected to a common node (320N) of the second sub circuit (310N) with a first terminal. For each capacitor (2C.sub.u, C.sub.u) of the first plurality of capacitors, the first sub circuit (310P) comprises a first switch (S4) connected between the first input (V.sub.inP) of the SAR ADC and a second terminal of that capacitor, a second switch (S.sub.2) connected between a first reference-voltage input (V.sub.rP) and the second terminal of that capacitor, a third switch (S.sub.1) connected between a second reference-voltage input (V.sub.rN) and the second terminal of that capacitor, and a capacitive device (X.sub.P) connected between the second input (V.sub.inN) of the SAR ADC and the second terminal of that capacitor. The second sub circuit is arranged in a similar way.

In a solid-state imaging element equipped with per-column ADCs, noise is reduced. A test signal source generates a test signal of a predetermined level. An analog-to-digital converter increases/decreases an analog signal according to an analog gain selected from among a plurality of analog gains, and converts the increased/decreased analog signal to a digital signal. An input switching section inputs, as the analog signal, either a test signal or a pixel signal to the analog-to-digital converter. A correction value calculation section obtains, on the basis of the test signal and the digital signal, a correction value for correcting an error in the selected analog gain, and outputs the correction value. A correction section corrects the digital signal according to the outputted correction value.