In an embodiment, a circuit includes N sensing channels. Each channel includes a first main sensing node and a second redundancy sensing node paired therewith. N analog-to-digital converters (ADCs) are coupled to the first sensing nodes, with digital processing circuits coupled to the N ADCs. A pair of multiplexers are coupled to the second sensing nodes and to the N ADCs with a further ADC coupled to the output of the second multiplexer. An error checking circuit is coupled to the outputs of the second multiplexer and the further ADC to compare, at each time window in a sequence of N time windows, a first digital value and a second digital value resulting from conversion to digital of: an analog sensing signal at one of the first sensing nodes, and an analog sensing signal at the second sensing node paired with the selected one of the first sensing nodes.

The systems and methods discussed herein related to digital to analog conversion. A digital to analog conversion circuit can includes a digital input, an analog output, and a cell array. The digital to analog converter can also include an integrator, an analog to digital converter (ADC), and a summer coupled to the ADC, and an adaptation circuit coupled to the summer. The adaption circuit provides controls signals to the cell array.

An analog-to-digital conversion (ADC) system is operated with a duty cycle. During the ON period, the ADC circuits perform analog-to-digital conversions of an analog input signal. During the Standby period, the ADC system is in either a standby state or a foreground calibration state. The ADC system operates in a reduced-power mode in the standby state. In the foreground calibration state, the ADC system performs a portion of a foreground calibration cycle during a calibration time slot. The foreground calibration cycle is performed over multiple calibration time slots. The foreground calibration cycle and the calibration time slots are configurable by changing the values of control registers that represent calibration parameters.

A TI-ADC (50) comprising a group of sub-ADCs (A.sub.1-A.sub.M+N) is disclosed. During operation, M≥2 of the sub-ADCs (A.sub.1-A.sub.M+N) are simultaneously operated for converting M respective consecutive input signal samples of the TI-ADC (50) from an analog to a digital representation. The total number of sub-ADCs (A.sub.1-A.sub.M+N) in the group is M+N, N≥1. The TI-ADC (50) comprises error-estimation circuitry (60) for estimating errors of the sub-ADCs (A.sub.1-A.sub.M+N). Furthermore, the TI-ADC (50) comprises a control circuit (55) configured to, for each input signal sample, assign which sub-ADC (A.sub.1-A.sub.M+N) is to operate on that input signal sample. The control circuit (55) is configured to, for sub-ADCs (A.sub.k.sub.1) in a first subset of the group of sub-ADCs (A.sub.1-A.sub.M+N), which are subject to error estimation by the error-estimation circuitry (60), perform the assignment according to a first scheme. Moreover, the control N circuit (55) is configured to, for sub-ADCs (A.sub.k.sub.2) in a second subset of the group of sub-ADCs (A.sub.1-A.sub.M+N), which are not subject to error estimation by the error-estimation circuitry (60), perform the assignment according to a second scheme, different from the first scheme.

An AD converter includes a plurality of analog input terminals, a reference signal generation circuit that generates an analog reference signal, a sample-and-hold unit that includes a plurality of sample-and-hold circuits sampling the analog reference signal or one of analog input signals from the analog input terminals, a control unit that controls the sample-and-hold unit, and a conversion unit that converts an output signal from the sample-and-hold unit into a digital signal. The control unit controls the sample-and-hold unit to perform the output operation for analog input signal and the sampling operation for the analog reference signal.

A current output module includes a current output section configured to output a current, an AD conversion circuit configured to convert a detection voltage, which is a voltage according to the current output from the current output section, into a digital value, a controller configured to control a current output from the current output section on the basis of the digital value of the detection voltage output from the AD conversion circuit, and a reference voltage generator configured to generate a plurality of reference voltages. The controller includes a processor configured to cause the AD conversion circuit to convert each of the plurality of reference voltages into a digital value, and a corrector configured to calibrate the AD conversion circuit on the basis of each digital value obtained by conversion of the plurality of reference voltages.

A N-bit continuous-time sigma-delta modulator, SDM, (800) includes an input configured to receive an input analog signal (302); a first summing junction (304) configured to subtract a feedback analog signal (303) from the input analog signal (302); a loop filter (306) configured to filter an output signal from the first summing junction (304): an N-bit analog-to-digital converter, ADC, comprising at least one 1-bit ADC configured to convert the filtered analog output signal (309) to a digital output signal (314) where each 1-bit ADC comprises at least one pair of comparator latches (336, 356); and a feedback path (316) for routing the digital output signal to the first summing junction (304). The feedback path (316) includes a plurality of digital-to-analog converters, DACs, configured to convert the digital output signal (314) to an analog form. The ADC comprises or is operably coupled to, a calibration circuit (650, 840) coupled to an input and an output of the at least one pair of comparator latches (336, 356) and configured to apply respective calibration signals to individual comparator latches of the at least one pair of comparator latches (336, 356) in a time-Interleaved manner, and calibrate a comparator error of the comparator latches in response to a latched output of the respective calibration signals.

A digital-to-analog conversion system is provided. The digital-to-analog conversion system includes a digital-to-analog converter configured to receive a pre-distorted digital signal from a digital circuit, and to generate an analog signal based on the pre-distorted digital signal. Further, the digital-to-analog conversion system includes a feedback loop for providing a digital feedback signal to the digital circuit. The feedback loop includes an analog-to-digital converter configured to generate the digital feedback signal based on the analog signal, and wherein a sample rate of the analog-to-digital converter is lower than a sample rate of the digital-to-analog converter.

Methods and systems are described for generating a process-voltage-temperature (PVT)-dependent reference voltage at a reference branch circuit based on a reference current obtained via a band gap generator and a common mode voltage input, generating a PVT-dependent output voltage at an output of a static analog calibration circuit responsive to the common mode voltage input and an adjustable current, adjusting the adjustable current through the static analog calibration circuit according to a control signal generated responsive to comparisons of the PVT-dependent output voltage to the PVT-dependent reference voltage, and configuring a clocked data sampler with a PVT-calibrated current by providing the control signal to the clocked data sampler.

Methods and systems are described for generating a process-voltage-temperature (PVT)-dependent reference voltage at a reference branch circuit based on a reference current obtained via a band gap generator and a common mode voltage input, generating a PVT-dependent output voltage at an output of a static analog calibration circuit responsive to the common mode voltage input and an adjustable current, adjusting the adjustable current through the static analog calibration circuit according to a control signal generated responsive to comparisons of the PVT-dependent output voltage to the PVT-dependent reference voltage, and configuring a clocked data sampler with a PVT-calibrated current by providing the control signal to the clocked data sampler.