A system and method for equalization of a linear or non-linear system. The system includes an adder configured to add an analog reference signal and an input signal, a processing system configured to process a sum of the analog reference signal and the input signal, a non-linear equalizer (NLEQ) configured to process an output of the processing system to remove a distortion incurred by the processing system, a calibration circuitry configured to generate a reconstructed reference signal in digital domain based on measurement of the analog reference signal, and generate coefficients for the NLEQ based on the reconstructed reference signal and the output of the processing system, and a subtractor configured to subtract the reconstructed reference signal from an output of the NLEQ. The analog reference signal may be a sinusoid including single or multiple tones of sinusoids. The non-linear system may be an analog-to-digital converter (ADC).

Methods and systems are described for generating a process-voltage-temperature (PVT)-dependent reference voltage at a reference branch circuit based on a reference current obtained via a band gap generator and a common mode voltage input, generating a PVT-dependent output voltage at an output of a static analog calibration circuit responsive to the common mode voltage input and an adjustable current, adjusting the adjustable current through the static analog calibration circuit according to a control signal generated responsive to comparisons of the PVT-dependent output voltage to the PVT-dependent reference voltage, and configuring a clocked data sampler with a PVT-calibrated current by providing the control signal to the clocked data sampler.

Input circuitry for an analog-to-digital converter (ADC) is provided. The input circuitry includes a calibration signal source configured to output a calibration signal for the ADC and an analog circuitry configured to receive and process an analog input signal for the ADC. The analog circuitry is further configured to generate a combined signal by combining the analog input signal and the calibration signal. The input circuitry further includes a buffer amplifier coupled to the analog circuitry and configured to supply a buffered signal to the ADC based on the combined signal. Further, the input circuitry includes neutralization circuitry configured to generate, based on the calibration signal, a neutralization signal for mitigating an unwanted signal component related to a limited reverse isolation of the analog circuitry. The neutralization circuitry is further configured to supply the neutralization signal to at least one of an input node and an intermediate node of the analog circuitry.

The invention relates to a circuit arrangement comprising a control device, an input circuit for applying an input signal, a conditioning circuit electrically connected to the input circuit for converting the input signal into a measured signal, an analog-to-digital converter electrically connected to the conditioning circuit for converting the measured signal into a digital value, and a reference source that outputs a known reference signal. In this respect, a first switching apparatus is provided that selectively separate the input signal from the conditioning circuit or supplies it to the conditioning circuit and a second switching apparatus is provided that selectively supplies the reference signal to the input circuit or separates it from the input circuit, wherein the control device is configured to determine an offset error and to determine a gain error of the circuit arrangement.

A digital to analog conversion, DAC, device for converting digital signals to analog signals comprises a RF output for outputting the analog signals, a thermometer segment comprising a first number of data slices and a second number calibration slices, and a calibration controller, which electrically disconnects one of the data slices from the RF output and at the same time connects one of the calibration slices to the RF output as replacement slice for the respective data slice and performs a calibration of the disconnected data slice.

An analog-to-digital conversion (ADC) system is operated with a duty cycle. During the ON period, the ADC circuits perform analog-to-digital conversions of an analog input signal. During the Standby period, the ADC system is in either a standby state or a foreground calibration state. The ADC system operates in a reduced-power mode in the standby state. In the foreground calibration state, the ADC system performs a portion of a foreground calibration cycle during a calibration time slot. The foreground calibration cycle is performed over multiple calibration time slots. The foreground calibration cycle and the calibration time slots are configurable by changing the values of control registers that represent calibration parameters.

The systems and methods discussed herein related to digital to analog conversion. A digital to analog conversion circuit can includes a digital input, an analog output, and a cell array. The digital to analog converter can also include an integrator, an analog to digital converter (ADC), and a summer coupled to the ADC, and an adaptation circuit coupled to the summer. The adaption circuit provides controls signals to the cell array.

Techniques that enable calibration of digital-to-analog Converters (DACs) with minimal processing overhead. A single frequency bin can be used to calibrate errors between bits. A low frequency feedback path can be included into a low frequency low power ADC to determine the error signal that exists in the calibration bin. The bits are calibrated when this error signal is minimized. The calibration techniques described provide an extremely efficient and optimal calibration at the DAC output of both static and dynamic errors.

In an embodiment, a circuit includes N sensing channels. Each channel includes a first main sensing node and a second redundancy sensing node paired therewith. N analog-to-digital converters (ADCs) are coupled to the first sensing nodes, with digital processing circuits coupled to the N ADCs. A pair of multiplexers are coupled to the second sensing nodes and to the N ADCs with a further ADC coupled to the output of the second multiplexer. An error checking circuit is coupled to the outputs of the second multiplexer and the further ADC to compare, at each time window in a sequence of N time windows, a first digital value and a second digital value resulting from conversion to digital of: an analog sensing signal at one of the first sensing nodes, and an analog sensing signal at the second sensing node paired with the selected one of the first sensing nodes.

A TI-ADC (50) comprising a group of sub-ADCs (A.sub.1-A.sub.M+N) is disclosed. During operation, M≥2 of the sub-ADCs (A.sub.1-A.sub.M+N) are simultaneously operated for converting M respective consecutive input signal samples of the TI-ADC (50) from an analog to a digital representation. The total number of sub-ADCs (A.sub.1-A.sub.M+N) in the group is M+N, N≥1. The TI-ADC (50) comprises error-estimation circuitry (60) for estimating errors of the sub-ADCs (A.sub.1-A.sub.M+N). Furthermore, the TI-ADC (50) comprises a control circuit (55) configured to, for each input signal sample, assign which sub-ADC (A.sub.1-A.sub.M+N) is to operate on that input signal sample. The control circuit (55) is configured to, for sub-ADCs (A.sub.k.sub.1) in a first subset of the group of sub-ADCs (A.sub.1-A.sub.M+N), which are subject to error estimation by the error-estimation circuitry (60), perform the assignment according to a first scheme. Moreover, the control N circuit (55) is configured to, for sub-ADCs (A.sub.k.sub.2) in a second subset of the group of sub-ADCs (A.sub.1-A.sub.M+N), which are not subject to error estimation by the error-estimation circuitry (60), perform the assignment according to a second scheme, different from the first scheme.