Provided are a Time-Interleaved Successive Approximation Register Analog-to-Digital Converter, TISAR ADC, and a calibration method thereof. The calibration method for the TISAR ADC may include: sampling an analog signal input into the TISAR ADC to generate a reference digital signal (S130); according to the reference digital signal and output digital signals generated by analog-to-digital conversion sub-modules of the TISAR ADC, obtaining capacitor array calibration parameters and time delay calibration parameters of the analog-to-digital conversion sub-modules; adjusting capacitor arrays of the corresponding analog-to-digital conversion sub-modules according to the capacitor array calibration parameters, respectively; and adjusting time delays of the corresponding analog-to-digital conversion sub-modules according to the time delay calibration parameters, respectively.

An auto calibration method used in switching converters with constant on-time control. The auto calibration method includes: generating a periodical clock signal with a predetermined duty cycle; providing a first voltage and a second voltage to an on-time control circuit to generate an on-time control signal based on the first and second voltage; providing the clock signal and on-time control signal to a logic circuit to generate a switch control signal based on the clock signal and on-time control signal; comparing the duty cycle of the switch control signal with the duty cycle of the clock signal to adjust a calibration code signal; and adjusting circuit parameters of the on-time control circuit in accordance with the calibration code signal.

A digital phase-locked loop (DPLL) may include a time-to-digital converter (TDC) to provide a phase error signal, a frequency-divider to perform frequency division on an output signal to generate a frequency-divided output signal, a delta-sigma-modulator (DSM) to provide a test signal that represents a quantization error of the DSM, and a digital-to-time converter (DTC) to at least partially remove the quantization error from the frequency-divided output signal based on the test signal to generate the feedback signal. The DPLL may include a circuit to cause the DTC to provide a percentage of the quantization error such that the percentage of the quantization error is in the phase error signal, and a TDC calibration component to calibrate the TDC by applying a gain adjustment factor to the TDC. The gain adjustment factor may be based on the test signal and the phase error signal including the percentage of the quantization error.

A calibration system comprises an actuator circuit comprising a first delay circuit that receives a plurality of data pulses and a second delay circuit that receives the pulses, wherein one of the first and second delay circuits delays the data pulses independently of the other of the first and second delay circuits; a data switch that receives an output of the actuator circuit including delay data signals of the data pulses from the first and second delay circuits and switches and outputs a plurality of local oscillator (LO) signals for output as a controlled LO signal according to control signals of the delay data signals and applied to the data switch. At least one calibration switch receives the output of the actuator circuit and the plurality of LO+ and LO− signals, and outputs a second controlled LO signal output to a sense circuit.

A clock product includes a time-to-digital converter responsive to an input clock signal, a reference clock signal, and a time-to-digital converter calibration signal. The time-to-digital converter includes a coarse time-to-digital converter and a fine time-to digital converter. The clock product includes a calibration circuit including a phase-locked loop. The calibration circuit is configured to generate the time-to-digital converter calibration signal. The clock product includes a controller configured to execute instructions that cause the phase-locked loop to generate an error signal for each possible value of a fine time code of a digital time code generated by the time-to-digital converter and to average the error signal over multiple clock cycles to generate an average error signal.

A composite analog-to-digital converter (ADC) has a low resolution ADC configured to receive and digitize analog data, the low resolution ADC having a low resolution and a high operating speed, one or more high resolution ADCs configured to receive and digitize the analog data, the one or more high resolution ADCs having a resolution higher than the low resolution ADC, and an operating speed lower than the high operating speed of the low resolution ADC, a sample clock generator to provide a sample clock signal to the low resolution ADC and to a clock divider, a mixer to receive the analog data and connected to the one or more high resolution ADCs, a local oscillator connected to the mixer to allow the one or more high resolution ADCs to be tuned to sample a portion of a spectrum of the first ADC. A test and measurement instrument contains a composite ADC. A method of operating a composite analog-to-digital converter (ADC), includes receiving an analog signal at a low resolution ADC that operates at a high speed, receiving the analog signal at one or more high resolution ADCs that operate at a resolution higher than the low resolution ADC and at a lower speed than the operating speed of the low resolution ADC, tuning the high resolution ADC to phase align and time align a signal path for the one or more high resolution ADCs to the signal path for the low resolution ADC, producing a spectrum from the low resolution ADC, and producing a portion of the spectrum from the one or more high resolution ADCs.

A digital-to-analog conversion device and method are provided. The control module is configured to split the input digital signal into n intermediate digital portions, divide the n intermediate digital portions by the corresponding conversion coefficients to obtain n intermediate digital signals and transmit the n intermediate digital signals to the n conversion modules. The n intermediate digital portions increase progressively. The conversion module is configured to perform digital-to-analog conversion on an intermediate digital signal to obtain a result including the conversion coefficient of the conversion module. The adder is configured to add output signals of the n conversion modules to obtain an analog signal. The feedback module is configured to obtain a feedback signal according to the analog signal. The control module is further configured to adjust the allocation of the n intermediate digital portions according to a target digital signal and the feedback signal.

Systems and methods for measurement and management are disclosed that provide complex measurements cost-effectively at very high accuracy. These methods and systems in some cases achieve measurement accuracy exceeding the accuracy of the reference standards they rely on, and eliminate expensive and disadvantageous recalibration procedures. The accurate measurements are integrated with management functions, applying the measurement data to meet objectives of the integrated system and workflow goals of its user. The disclosed systems and methods comprise an explicit or expressly represented model both of themselves and of candidate external systems to be measured and managed. The models may be configured and reconfigured by the owner-user through either local or remote means. The system intelligently reconfigures itself to adapt dynamically to the conditions of measurement and the user's and system's goals at each moment. In an embodiment, the system includes high-accuracy and reconfigurable components including a meter or control head adapted for user precision assembly and maintenance that computes and displays or communicates the measurements, displaying measurements in desired units, grouping functions according to ergonomic and cognitive principles based on the activity and workflow of a user in relation to the internal model. The use of models permits the system to compute and provide complex and inferred measurements of ultimate interest to the user, including quantities that cannot be directed measured and only can be determined through reasoning or computation by applying models to raw measurement data. The precision-assembly modular electromechanical design further permits an owner-user to precisely assemble, maintain, modify the apparatus and calibrate the equipment for accuracy.

Certain aspects of the present disclosure provide a digital-to-analog converter (DAC) system. The DAC system generally includes a plurality of current sources, a plurality of calibration DACs, each coupled to a respective one of the plurality of current sources, a reference current source, and a current mirror having a first branch selectively coupled to the plurality of current sources, wherein a second branch of the current mirror is coupled to the reference current source. The DAC system also includes a first error DAC selectively coupled to the first branch and the second branch of the current mirror, and a second error DAC selectively coupled to the first branch and the second branch of the current mirror.

An AD converter with self-calibration function that does not require an instrument for calibration, and includes: a reference voltage unit that generates a reference voltage; a summation and conversion unit that has two or more unit voltages serving as units of amount of change in a summed voltage, and during conversion, sums up any one unit voltage of the two or more unit voltages until the summed voltage exceeds the reference voltage, with an input voltage being an initial value of the summed voltage; and a control unit including a calibration control section that calibrates the two or more unit voltages and an offset voltage of a comparator at a time of calibration, and a conversion control section that determines a polarity of the offset voltage of the comparator and thereafter converts the input voltage to a digital value during conversion.