An ADC system comprises a coarse ADC for determining a coarse word representing an input signal, and an incremental ADC for determining a fine word based on a combination of the input signal and a feedback signal. A first combiner generates a first intermediate output word by joining the coarse word and the fine word. A feedback path generates the feedback signal based on the first intermediate output word. A decimation filter generates a second intermediate output word by filtering the first intermediate output word. A correction block determines a correction word based on the coarse word, on the first and the second predetermined number of bits and conversion parameters of the incremental ADC. A second combiner generates an output word by addition of the second intermediate output word and the correction word.

A system and method for equalization of a linear or non-linear system. The system includes an adder configured to add an analog reference signal and an input signal, a processing system configured to process a sum of the analog reference signal and the input signal, a non-linear equalizer (NLEQ) configured to process an output of the processing system to remove a distortion incurred by the processing system, a calibration circuitry configured to generate a reconstructed reference signal in digital domain based on measurement of the analog reference signal, and generate coefficients for the NLEQ based on the reconstructed reference signal and the output of the processing system, and a subtractor configured to subtract the reconstructed reference signal from an output of the NLEQ. The analog reference signal may be a sinusoid including single or multiple tones of sinusoids. The non-linear system may be an analog-to-digital converter (ADC).

A phase-shifted sampling module for sampling a signal is described. The phase-shifted sampling module includes a primary sampler module, an ADC module, and an equalization module. The primary sampler module includes an analog signal input, a first signal path, and a second signal path. The equalization module includes a primary sampler equalizer sub-module. The primary sampler equalizer sub-module is configured to compensate low-frequency mismatches between the first signal path and the second signal path. Further, a method for determining filter coefficients of an equalization module of a phase-shifted sampling module is described.

The present invention discloses a DAC method having signal calibration mechanism. A first conversion circuit generates a first analog signal according to an input digital signal. A second conversion circuit generates a second analog signal according to the input digital signal and a pseudo-noise digital signal. An echo transmission circuit processes a signal on an echo path to generate an echo signal. A first and a second calibration circuits generate a first and a second calibration signals. A calibration parameter calculation circuit performs calculation according to a difference between the echo signal and a sum of the first and the second calibration signals and related path information to generate a first and a second offsets. The first and the second calibration circuits converge first and second response coefficients and update a first and a second codeword offset tables according to the first and the second offsets.

A pipeline analog to digital converter includes converter circuitries and a calibration circuitry. The converter circuitries sequentially convert an input signal into a plurality of first digital codes, in which a first converter circuitry in the converter circuitries is configured to perform a quantization according to a first signal to generate a first corresponding digital code in the first digital codes, and the first signal is a signal, which is processed by the first converter circuitry, of the input signal and a previous stage residue signal. The calibration circuitry combines the first digital codes to output a second digital code, detects whether the quantization is completed to generate control signals, and determines whether to set the second digital code to be a second corresponding digital code in predetermined digital codes according to the control signals.

An analog-to-digital converter (ADC) is described. This ADC includes a conversion circuit with multiple bit-conversion circuits. During operation, the ADC may receive an input signal. Then, the conversion circuit may asynchronously perform successive-approximation-register (SAR) analog-to-digital conversion of the input signal using the bit-conversion circuits, where the bit-conversion circuits to provide a quantized representation of the input signal. For example, the bit-conversion circuits may asynchronously and sequentially perform the SAR analog-to-digital conversion to determine different bits in the quantized representation of the input signal. Moreover, the ADC may selectively perform self-calibration of a global delay of the bit-conversions circuits. Note that the timing self-calibration may be iterative and subject to a constraint that a maximum conversion time is less than a target conversion time.

An apparatus for correcting a mismatch between a first segment and a second segment of a Digital-to-Analog Converter, DAC, is provided. The first segment generates a first contribution to an analog output signal of the DAC based on a first number of bits of a digital input word for the DAC converter, and the second segment generates a second contribution to the analog output signal based on a second number of bits of the digital input word. The apparatus comprises an input configured to receive the digital input word. Further, the apparatus comprises a first processing circuit for the first number of bits comprising a first filter configured to modify the first number of bits in order to generate first modified bits, and a second processing circuit for the second number of bits comprising a second filter configured to modify the second number of bits in order to generate second modified bits. The apparatus additionally comprises an output configured to output a modified digital input word for the DAC. The modified digital input word is based on the first modified bits and the second modified bits.

An ADC system comprises a coarse ADC for determining a coarse word representing an input signal, and an incremental ADC for determining a fine word based on a combination of the input signal and a feedback signal. A first combiner generates a first intermediate output word by joining the coarse word and the fine word. A feedback path generates the feedback signal based on the first intermediate output word. A decimation filter generates a second intermediate output word by filtering the first intermediate output word. A correction block determines a correction word based on the coarse word, on the first and the second predetermined number of bits and conversion parameters of the incremental ADC. A second combiner generates an output word by addition of the second intermediate output word and the correction word.

An example apparatus includes: an analog input; a resistor circuit including a first reference output and a second reference output; a first amplifier including a first analog input, a first reference input, and a first amplifier output, the first analog input coupled to the analog input, the first reference input coupled to the first reference output; a second amplifier including a second analog input, a second reference input, and a second amplifier output, the second analog input coupled to the analog input, the second reference input coupled to the second reference output; a first comparator including a first comparator input, the first comparator input coupled to the first amplifier output; and a second comparator including a second comparator input, the second comparator input coupled to the second amplifier output; a first multiplexer including a first multiplexer input and a first residue output, the first multiplexer input coupled to the first amplifier output; and a second multiplexer including a second multiplexer input and a second residue output, the second multiplexer input coupled to the second amplifier output.

The present disclosure relates to implementations of a method and a system for calibrating the system that includes analog-to-digital converters (ADCs). The method, performed on the system's corresponding components include, providing, from a signal generator, a first signal during a calibration mode. Parallel ADCs provide ADC outputs associated with the first signal. First parallel filters provide derivative signals associated with the ADC outputs. Second and third parallel filters provide first and second band-stop filtered signals associated with the ADC outputs and the derivative signals, respectively. The disclosure includes multiplying the first and the second band-stop filtered signals and selecting a portion of the multiplied signals that are accumulated for storage. The system incorporating these components performing these features is, accordingly, calibrated.