A memory device performs a convolution operation. The memory device includes first to N-th processing elements (PEs), a first analog-to-digital converter (ADC), a first shift adder, and a first accumulator. The first to N-th PEs, where N is a natural number equal to or greater than 2, are respectively associated with at least one weight data included in a weight feature map and are configured to perform a partial convolution operation with at least one input data included in an input feature map. The first ADC is configured to receive a first partial convolution operation result from the first to N-th PEs. The first shift adder shifts an output of the first ADC. The first accumulator accumulates an output from the first shift adder.

Methods for use in a measurement system. Some embodiments comprise at least one sensor unit and a control unit, wherein the at least one sensor unit is configured to detect a physical quantity and to form a sensor data signal. The method comprises, at the control unit, receiving a data receive signal from the sensor unit, and interpreting the data receive signal to be one of at least the sensor data signal and another data signal, wherein the interpreting is based on an attribute information intrinsic to the data receive signal. Furthermore, there is a sensor unit for use in measurement data acquisition, an apparatus configured to control a measurement data acquisition, a measurement system for use in measurement data acquisition, and a medium incorporating a sequence of operation steps that, when executed, perform a method for use in a measurement system for data acquisition.

The present invention provides a signal processing circuit including a control unit, a transmission drive unit, an analog switch array, a signal amplification unit, a detection integration unit that are connected in sequence, and a transceiver antenna connected to the analog switch array. The control unit includes an analog-to-digital converter. The signal processing circuit further includes a level conversion unit arranged between the analog-to-digital converter and the signal amplification unit, the level conversion unit is configured to linearly convert signals received by the transceiver antenna, and transmit the linearly converted signals to the analog-to-digital converter. The signal processing circuit has advantages of low cost, fast handwriting speed, and less cursor wobble. The present invention also provides a position detecting device using the same.

A method for measuring a complex impedance of a plurality of battery cells in a battery pack comprises controlling an excitation current through the plurality of battery cells in the battery pack; receiving, in a single common measurement circuit, a plurality of voltage signals corresponding to the plurality of battery cells; measuring the excitation current; and calculating a complex impedance of each of the battery cells in the plurality of battery cells based on the plurality of voltage signals and the measured excitation current in a single measurement cycle using either one analog-to-digital converter (ADC) per battery cell or two matched ADCs per battery cell.

A signal control device includes a charge/discharge circuit, a sampling capacitor, and an AC conversion circuit. The charge/discharge circuit is capable of charging or discharging the sampling capacitor. The AC conversion circuit performs an AD conversion by converting an analog voltage value charged in the sampling capacitor into an AD conversion value that is a digital value. After a charge operation or a discharge operation to the sampling capacitor with the charge/discharge circuit, the AD conversion circuit performs the AD conversion, and a malfunction of the charge/discharge circuit is determined based on a diagnosis result of the AD conversion value.

In accordance with some embodiments of the present disclosure, an apparatus including a crossbar circuit is provided. The crossbar circuit may include a plurality of cross-point devices with programmable conductance, a transimpedance amplifier (TIA), and an analog-to-digital converter (ADC). The TIA is configured to produce an output voltage based on an input current corresponding to a summation of current from a first plurality of the cross-point devices. The ADC is configured to generate a digital output corresponding to a digital representation of the output voltage of the TIA. To generate the digital output, the ADC is to generate, using a comparator, a first plurality of bits (e.g., MSBs) of the digital output by performing a coarse conversion process and a second plurality of bits (e.g., LSBs) of the digital output by performing a fine conversion process on a sample-and-hold voltage produced in the coarse conversion process.

An analog circuit including a voltage regulator, at least one analog-to-digital convertor (ADC), at least one comparator and a multiplexer is provided. The voltage regulator generates an output voltage. The at least one ADC generates at least one digital signal. The multiplexer is configured to conduct the at least one comparator to either the voltage regulator or the at least one ADC. When the voltage regulator is triggered, the multiplexer conducts the at least one comparator to the voltage regulator, and the voltage regulator generates the output voltage according to an output of the at least one comparator. When the at least one ADC is triggered, the multiplexer conducts the at least one comparator to the at least one ADC, and the at least one ADC generates the at least one digital signal according to the output of the at least one comparator.

An electronic device includes analog-to-digital converters each configured to receive an analog input signal and output a digital output signal corresponding to the analog input signal, an analog input signal generator configured to generate analog input signals provided to each analog-to-digital converter based on input voltages and weight data, an input signal distribution information generator configured to generate input signal distribution information indicating a distribution of the analog input signals for each of the analog-to-digital converters, an analog-to-digital converter group classifier configured to classify the analog-to-digital converters into a plurality of first analog-to-digital converter groups based on the input signal distribution information, and an analog-to-digital converter input range optimizer configured to determine an input range of each first analog-to-digital converter group based on the input signal distribution information, and each analog-to-digital converter is configured to operate according to an input range of a corresponding first analog-to-digital converter groups.

A Light Detection and Ranging (LIDAR) receiver includes a photodetector array configured to generate a plurality of electrical signals; a receiver circuit including a plurality of readout channels, configured to read out the plurality of electrical signals from the photodetector array, and a plurality of multibit ADCs, wherein each of the plurality of readout channels includes a different one of the plurality of multibit ADCs, and each of the plurality of multibit ADCs is configured to convert at least one of the plurality of electrical signals into an ADC data sample such that the plurality of multibit ADCs generate a sequence of ADC data samples; an encoder coupled to the plurality of readout channels and configured to receive the sequence of ADC data samples and generate a compressed data packet based on the sequence of ADC data samples; and a communication interface configured to transmit the compressed data packet.

A system is provided that includes electrodes configured to be implanted in a body, and a pulse generator (PG) circuitry to deliver a stimulus to one or more of the electrodes. The system also includes sensing circuitry configured to define a sensing channel between one or more of the electrodes to sense signals indicative of a physiologic activity of interest, and the sensing circuitry further configured to collect a calibration signal over the sensing channel. The sensing circuitry and PG circuitry are housed within an implantable medical device (IMD). The system also includes one or more processors configured to determine a signal characteristic of interest (COI) of the calibration signal. The one or more processors are also configured to compare a signal COI of the stimulus to the signal COI of the calibration signal, and adjust a parameter of the sensing circuitry or PG circuitry based on the comparison.