An analog-to-digital converter includes: a voltage-current converter receiving an analog input voltage, generating a first digital signal from the analog input voltage, and outputting a residual current remaining after the first digital signal; a current-time converter converting the residual current into a current time in a time domain; and a time-digital converter receiving the residual time, and generating a second digital signal from the residual time, wherein the first digital signal and the second digital signal are sequences of digital codes representing respective signal levels of the analog input voltage.

Systems and methods for interrogating sensing systems utilising bursts of samples. Bursts of samples correspond to optical pulses returning from optical sensors, where pulses are spaced at a period significantly longer than the pulse width, giving irregular sample spacing. The interrogation system and method processes the irregular busts of samples to recover phase information from received signals.

Systems and methods for interrogating sensing systems utilising bursts of samples. Bursts of samples correspond to optical pulses returning from optical sensors, where pulses are spaced at a period significantly longer than the pulse width, giving irregular sample spacing. The interrogation system and method processes the irregular busts of samples to recover phase information from received signals.

An ADC system comprises a coarse ADC for determining a coarse word representing an input signal, and an incremental ADC for determining a fine word based on a combination of the input signal and a feedback signal. A first combiner generates a first intermediate output word by joining the coarse word and the fine word. A feedback path generates the feedback signal based on the first intermediate output word. A decimation filter generates a second intermediate output word by filtering the first intermediate output word. A correction block determines a correction word based on the coarse word, on the first and the second predetermined number of bits and conversion parameters of the incremental ADC. A second combiner generates an output word by addition of the second intermediate output word and the correction word.

An ADC system comprises a coarse ADC for determining a coarse word representing an input signal, and an incremental ADC for determining a fine word based on a combination of the input signal and a feedback signal. A first combiner generates a first intermediate output word by joining the coarse word and the fine word. A feedback path generates the feedback signal based on the first intermediate output word. A decimation filter generates a second intermediate output word by filtering the first intermediate output word. A correction block determines a correction word based on the coarse word, on the first and the second predetermined number of bits and conversion parameters of the incremental ADC. A second combiner generates an output word by addition of the second intermediate output word and the correction word.

An analog-to-digital conversion device is provided that includes a front SAR ADC and a plurality of rear SAR ADCs. The front SAR ADC is configured to convert an analog input signal into a group of higher bits of a digital output signal in response to different time periods. Each of the rear SAR ADCs is electrically coupled to the front SAR ADC and is configured to receive the analog input signal and the corresponding group of higher bits in response to the different time periods. The rear SAR ADCs convert the analog input signal into a group of lower bits of the digital output signal corresponding to the time period of the group of higher bits.

Technologies are provided for time-to-digital conversion without reliance on a clocking signal. Some embodiments of the technologies include a clockless TDC apparatus that can map continuous pulse-widths to binary bits represented via an iterative chaotic map (e.g., tent map, Bernoulli shift map, or similar). The clockless TDC apparatus can convert separated pulses to a single asynchronous digital pulse that turns on when a sensor detects a first pulse and turns off when the sensor detects a second pulse. The asynchronous digital pulse can be iteratively stretched and folded in time according to the chaotic map. The clockless TDC can generate a binary sequence that represents symbolic dynamics of the chaotic map. The process can be implemented by using an iterative time delay component until a precision of the binary output is either satisfied or overwhelmed by noise or other structural fluctuations of the TDC apparatus.

A data acquisition system comprises a signal processing chain including an analog-to-digital converter (ADC) circuit configured to: produce a digital output from an input signal; detect a specified signal feature of the input signal; and change an operating condition of an additional circuit of the signal processing chain in response to detecting the signal feature of the input signal.

A data acquisition system comprises a signal processing chain including an analog-to-digital converter (ADC) circuit configured to: produce a digital output from an input signal; detect a specified signal feature of the input signal; and change an operating condition of an additional circuit of the signal processing chain in response to detecting the signal feature of the input signal.

An AD converter includes: an integration unit 22 that uses an input voltage as an initial value and repeats an operation of integrating one or both of two types of unit voltages with the input voltage, thereby generating an integrated voltage; a switching threshold voltage unit 23 that includes two types of threshold voltages causing the operation of integrating to be terminated; a comparator 24 that compares the integrated voltage with the threshold voltages; an integration determination unit 11 that, before the operation of integrating is started, causes the comparator 24 to compare the input voltage with a rough adjustment threshold voltage corresponding to a larger one of the unit voltages; a unit voltage switching control unit 12 that, when the rough adjustment threshold voltage is larger than the input voltage, controls the integration unit 22 to generate the integrated voltage by using the two types of unit voltages; and a single unit voltage control unit 13 that, when the rough adjustment threshold voltage is smaller than the input voltage, controls the integration unit 22 to generate the integrated voltage by using only a smaller one of the unit voltages.