Technologies are provided for time-to-digital conversion without reliance on a clocking signal. Some embodiments of the technologies include a clockless TDC apparatus that can map continuous pulse-widths to binary bits represented via an iterative chaotic map (e.g., tent map, Bernoulli shift map, or similar). The clockless TDC apparatus can convert separated pulses to a single asynchronous digital pulse that turns on when a sensor detects a first pulse and turns off when the sensor detects a second pulse. The asynchronous digital pulse can be iteratively stretched and folded in time according to the chaotic map. The clockless TDC can generate a binary sequence that represents symbolic dynamics of the chaotic map. The process can be implemented by using an iterative time delay component until a precision of the binary output is either satisfied or overwhelmed by noise or other structural fluctuations of the TDC apparatus.

An analog-to-digital converter (ADC) having an input operable to receive an input voltage, V.sub.IN, and an output operable to output a digital code representative of V.sub.IN, the ADC including: a voltage-to-delay circuit having an input and an output, the input of the voltage-to-delay circuit coupled to the input of the ADC; a folding circuit having an input and an output, the input of the folding circuit coupled to the output of the voltage-to-delay circuit; and a time delay-based analog-to-digital converter backend having an input and a digital code output coupled to the output of the ADC, the input of the time delay-based analog-to-digital converter backend coupled to the output of the folding circuit.

An RF receiver including: a low noise amplifier adapted to be coupled to an antenna and having an output; a bandpass filter coupled to the output of the low noise amplifier and having a voltage signal output, V.sub.IN; a conversion and folding circuit; and an analog-to-digital converter for converting the earlier-arriving or later-arriving delay signals into a digital code representing the voltage signal. The conversion and folding circuit including: a voltage-to-delay converter block, including preamplifiers, for converting the voltage signal into delay signals; and a folding block, including logic gates coupled to the preamplifiers, for selecting earlier-arriving and later-arriving ones of the delay signals.

A method for light-to-digital conversion includes setting a time integrator circuit into a reference condition and starting to integrate charge from a sensor device for the duration of an integration time. An integration signal is generated and is indicative of the integrated charge. The integration signal is compared with an adjustable reference signal. A first count is generated when the comparison indicates that the integration signal has reached an integration range, wherein the integration range is defined by a low and a high voltage. A second count is generated when the comparison indicates that the integration signal has reached the adjustable reference signal. The adjustable reference signal is incremented in discrete steps when a second count has been generated. Then, the time integrator circuit is reset into the reference condition, when the comparison indicates that the integration signal has reached the integration range. The generated first counts is collected as first count signal and the generated second counts are collected as second count signal. Finally, a digital output signal is generated depending on the first count signal and the second count signal.

An analog-to-digital conversion circuit includes a first comparator, a second comparator and a counter circuit. The first comparator compares an analog signal with a ramp signal. The second comparator compares the analog signal with the ramp signal plus a predetermined offset. When a signal level of the ramp signal is less than a signal level of the analog signal, the counter circuit counts a number of clock cycles of a first clock signal to generate a first portion of a digital signal. When the signal level of the ramp signal plus the predetermined offset is greater than the signal level of the analog signal, the counter circuit counts a number of clock cycles of a second clock signal to generate a second portion of the digital signal. A frequency of the first clock signal is less than a frequency of the second clock signal.

An RF receiver including: an antenna cable of receiving an RF signal; a low noise amplifier coupled to the antenna and having an output; a bandpass filter coupled to the output of the low noise amplifier and having a voltage signal output, V.sub.IN; a conversion and folding circuit; and an analog-to-digital converter for converting the earlier-arriving or later-arriving delay signals into a digital code representing the voltage signal. The conversion and folding circuit having: a voltage-to-delay converter block, including preamplifiers, for converting the voltage signal into delay signals; and a folding block, including logic gates coupled to the preamplifiers, for selecting earlier-arriving and later-arriving ones of the delay signals; and

An A/D converter 1 includes a front stage A/D conversion unit (3) including a first A/D conversion unit (6) that receives an analog signal from a CMOS image sensor (100) and generates a first digital value (D1) and a first residual analog signal (V.sub.OPF) through a folding integration A/D conversion operation, and a second A/D conversion unit (7) that receives a first residual analog signal (V.sub.OPF) from the first A/D conversion unit (6) and generates a second digital value (D2) and a second residual analog signal (V.sub.OPC) through a cyclic A/D conversion operation, and a rear stage A/D conversion unit (4) that receives the second residual analog signal (V.sub.OPC) from the front stage A/D conversion unit (3) and generates a third digital value (D3) through an acyclic A/D conversion operation.

A conversion and folding circuit includes a voltage-to-delay converter block, including preamplifiers, for converting a voltage signal into delay signals, and a folding block, including logic gates coupled to the preamplifiers, for selecting earlier-arriving and later-arriving ones of the delay signals. If desired, the logic gates may include odd and even chains for outputting delay signals to first and second analog-to-digital converters. If desired, the conversion and folding circuit may include first and second chains, and a chain selection circuit for selectively outputting a delay signal from a desired one of the first and second chains.

An analog-to-digital conversion circuit includes a first comparator, a second comparator and a counter circuit. The first comparator compares an analog signal with a ramp signal. The second comparator compares the analog signal with the ramp signal plus a predetermined offset. When a signal level of the ramp signal is less than a signal level of the analog signal, the counter circuit counts a number of clock cycles of a first clock signal to generate a first portion of a digital signal. When the signal level of the ramp signal plus the predetermined offset is greater than the signal level of the analog signal, the counter circuit counts a number of clock cycles of a second clock signal to generate a second portion of the digital signal. A frequency of the first clock signal is less than a frequency of the second clock signal.

An analog-to-digital converter (ADC) includes: a set of comparators configured to provide comparison results based on an analog signal and respective reference thresholds for comparators of the set of comparators; digitization circuitry configured to provide a digital output code based on the comparison results and a mapping; and calibration circuitry. The calibration circuitry is configured to: receive the comparison results; determine if the analog signal is proximate to one of the respective reference thresholds based on the comparison results; in response to determining the analog signal is proximate to one of the respective reference thresholds, receive ADC values based on different pseudorandom binary sequence (PRBS) values being applied to the analog signal; determine an offset error based on the ADC values; and provide a comparator input offset calibration signal at a calibration circuitry output if the estimated offset error is greater than an offset error threshold.