A pipelined analog-to-digital converter and an output calibration method for the same. The pipelined analog-to-digital converter introduces an error calibration mechanism on the basis of traditional pipelined analog-to-digital converters through a control module, an equivalent gain error extraction module, an error storage module and a coding reconstruction module to compensate for gain errors and setup errors caused by operational amplifiers in a pipelined conversion module, so that the analog-to-digital conversion accuracy is improved, and requirements for the gain and bandwidth of the operational amplifier are relaxed, which can effectively reduce the power consumption of the analog-to-digital converter and the complexity of the corresponding analog circuit; a curve fitting method is adopted to obtain an ideal output sequence and then calculate errors; meanwhile, extraction and calibration of equivalent gain errors are all done in digital ways, and therefore accuracy thereof is high.

An analog-to-digital converter includes a primary converter and a secondary converter. The primary converter executes conversion processing to convert an analog input signal to a first digital signal through delta-sigma modulation. The secondary converter outputs a second digital signal by converting amplified analog output of a quantization error in the primary converter to the second digital signal.

An apparatus is disclosed for pipelined analog-to-digital conversion. In an example aspect, the apparatus includes a pipelined analog-to-digital converter (ADC). The pipelined ADC includes a first stage and a second stage. The first stage includes a sampler and a quantizer coupled to the sampler. The first stage also includes a current distribution circuit coupled to the sampler. The second stage includes a sampler coupled to the current distribution circuit and a quantizer coupled to the sampler of the second stage.

An ANC system includes an AD converter which performs AD conversion on an external noise signal, an ANC signal generator which generates an ANC signal for canceling a noise component arriving at the ears of a user based on an output signal of the AD converter, and a level detector which detects a level of the output signal and causes the ANC signal generator to power down in response to the level. The level detector measures a time for which the level is equal to or less than a predetermined first threshold value, causes the ANC signal generator or a portion of blocks of the AD converter to power down after the measured time exceeds a predetermined value, and causes the ANC signal generator or a portion of blocks of the AD converter to return from the power down when the level exceeds a predetermined second threshold value.

A system may include ADC circuitry. To test the performance of the ADC circuitry, the system may include ADC testing circuitry coupled to the ADC circuitry. In particular, the ADC testing circuitry may include reference voltage generation circuitry configured to generate reference voltages serving as test voltages for the ADC circuitry. The ADC circuitry may be coupled to a test input for receiving the test voltages via switching circuitry and may be coupled to a main data input for receiving system data via the switching circuitry. Testing may occur during an idling time period of the system and when the switching circuitry couples the test input to the ADC circuitry. Test input voltages corresponding to one or more stages in the ADC circuitry may be provided to the ADC circuitry, and corresponding output values from the ADC circuitry may be compared to an expected value and/or expected threshold values.

Cross-coupling of switched-capacitor output common-mode feedback capacitors in dynamic residue amplifiers is provided via a cross-coupled amplifier, comprising: a current source connected to a first node; a feedback capacitor connected to the first node and a second node; a feedback resistor connected between the second node and ground; an amplifier having an input connected to the second node; a gain transistor having: a drain connected to the first node; a source connected to ground; and a gate connected to an output of the amplifier; and a load capacitor connected to the first node and ground.

Numerous embodiments of analog neural memory arrays are disclosed. In one embodiment, an analog neural memory system comprises an array of non-volatile memory cells, wherein the cells are arranged in rows and columns, the columns arranged in physically adjacent pairs of columns, wherein within each adjacent pair one column in the adjacent pair comprises cells storing W+ values and one column in the adjacent pair comprises cells storing W− values, wherein adjacent cells in the adjacent pair store a differential weight, W, according to the formula W=(W+)−(W−). In another embodiment, an analog neural memory system comprises a first array of non-volatile memory cells storing W+ values and a second array storing W− values.

Herein disclosed is an example analog-to-digital converter (ADC) and methods that may be performed by the ADC. The ADC may derive a first code that approximates a combination of an analog input value of the ADC and a dither value for the ADC sampled on a capacitor array. The ADC may further derive a second code to represent a residue of the combination with respect to the first code applied to the capacitor array. The ADC may combine the numerical value of the first code and the numerical value of the second code to produce a combined code applied to the capacitor array for deriving a digital output code. Combining the numerical value of the first code and the numerical value of the second code in the digital domain can provide for greater analog-to-digital (A/D) conversion linearity.

The exemplified disclosure presents a successive approximation register analog-to-digital converter circuit that comprises a two-step (e.g., two-stage) analog-to-digital converter (ADC) that operates a 1st-stage successive approximation register (SAR) in the continuous time (CT) domain (also referred to as a “1-st stage CTSAR”) that then feeds a sampling operation location in the second stage. Without a front-end sampling circuit in the 1st-stage, the exemplary successive approximation analog-to-digital converter circuit can avoid high sampling noise associated with such sampling operation and thus can be configured with a substantially smaller input capacitor size (e.g., at least 20 times smaller) as compared to conventional Nyquist ADC with a front-end sample-and-hold circuit.

An analog-to-digital converter (ADC) includes a coarse ADC that receives an analog input voltage, generates a first digital signal based on the analog input voltage using a successive approximation register (SAR) method, and outputs a residual voltage remaining after the first digital signal is generated. The ADC further includes an amplifier that receives the residual voltage and a test voltage, generates a residual current by amplifying the residual voltage by a predetermined gain, and generates a test current by amplifying the test voltage by the gain. The ADC further includes a fine ADC that receives the residual current and generates a second digital signal based on the residual current using the SAR method, and an auxiliary path that receives the test current and generates a gain correction signal based on the test current. The gain of the amplifier is adjusted based on the gain correction signal.