An analog-to-digital converting device includes: a main analog-to-digital converter configured to convert an analog signal output from a sensor to a digital signal; and a monitoring unit configured to monitor the digital signal converted by the main analog-to-digital converter. The main analog-to-digital converter is provided by a special purpose IC arranged separately from a microcomputer for controlling the main analog-to-digital converter. The monitoring unit includes multiple sub analog-to-digital converters each of which having a conversion accuracy lower than that of the main analog-to-digital converter and converting the analog signal output from the sensor to a digital signal. The monitoring unit sets a predetermined threshold based on conversion values of the digital signals converted by the multiple sub analog-to-digital converters, and compares a conversion value of the digital signal converted by the main analog-to-digital converter with the predetermined threshold.

A light receiving unit receives a pulsed optical signal arriving from a search region. A branching unit generates, from a received light signal, a plurality of branch signals having signal intensities proportional to a signal intensity of the received light signal and different from one another. A conversion unit converts, from analog to digital, a signal fed via the individual path selected by a selection unit, and in accordance with a result of the conversion, a processing unit generates information regarding an object reflecting the optical signal. A control unit causes the selection unit to select one of the individual paths for which a determination unit determines that a magnitude of the fed signal is within an input range of the conversion unit and which provides the highest gain.

A circuit includes an operational amplifier and a resistor network coupled to an output of the operational amplifier. The resistor network includes a first set of resistors coupled between the output of the operational amplifier and a first node of the resistor network, wherein the resistors of the first set are electrically connected in series with each other, a second set of resistors coupled between the first node and a second node of the resistor network, wherein the resistors of the second set are electrically connected in series with each other and include a first number of resistors, a third set of resistors coupled between the second node and a third node of the resistor network, wherein the third node is coupled to a first voltage, and wherein the resistors of the third set are electrically connected in parallel with each other and include a second number of resistors, and a resistor coupled between the first node and the second node and arranged in parallel with the second set of resistors.

An analogue-to-digital converter (ADC), comprising: an adaptive whitening filter configured to filter an analogue input signal and output a whitened analogue input signal; a first converter configured to receive said whitened analogue input signal and output a whitened digital signal; a controller configured to adapt the whitening filter based on the received analogue input signal.

A circuit includes an operational amplifier and a resistor network coupled to an output of the operational amplifier. The resistor network includes a first set of resistors coupled between the output of the operational amplifier and a first node of the resistor network, wherein the resistors of the first set are electrically connected in series with each other, a second set of resistors coupled between the first node and a second node of the resistor network, wherein the resistors of the second set are electrically connected in series with each other and include a first number of resistors, a third set of resistors coupled between the second node and a third node of the resistor network, wherein the third node is coupled to a first voltage, and wherein the resistors of the third set are electrically connected in parallel with each other and include a second number of resistors, and a resistor coupled between the first node and the second node and arranged in parallel with the second set of resistors.

Example embodiments relate to time-interleaved analog-to-digital converters and conversion methods thereof. One embodiment includes a slope analog-to-digital converter. The slope analog-to-digital converter includes a sample and hold stage configured to sample an analog input signal at a sampling frequency. The slope analog-to-digital converter also includes a comparator downstream to the sample and hold stage configured to compare the analog input signal to a slope signal. Further, the slope analog-to-digital converter includes a digital logic configured to receive a counter value corresponding to a voltage level of the slope signal and to sample the counter value based upon the comparison, thereby generating a digital representation of the analog input signal based upon the comparison. The slope signal is asynchronous to the sampling frequency.

An analog-to-digital converter (ADC) configured to convert an analog signal to digital bits. The ADC includes a plurality of sub-ADCs that are cascaded in a pipeline. Each sub-ADC may be configured to sample an input signal that is fed to each sub-ADC and convert the sampled input signal to a pre-configured number of digital bits. Each sub-ADC except a last sub-ADC in the pipeline is configured to generate a residue signal and feed the residue signal as the input signal to a succeeding sub-ADC in the pipeline. At least one sub-ADC is configured to determine a most-significant bit (MSB) of the pre-configured number of digital bits while the input signal is sampled. The ADC may include a plurality of residue amplifiers for amplifying a residue signal. The sub-ADCs may be successive approximation register (SAR) ADCs or flash ADCs.

An input buffer circuit for an analog-to-digital converter is provided. The input buffer circuit includes a buffer amplifier. The buffer amplifier includes a first input node and a second input node each configured to receive a respective one of a first input signal and a second input signal forming a differential input signal pair for the analog-to-digital converter. The buffer amplifier further includes a first output node and a second output node each configured to output a respective one of a first buffered signal and a second buffered signal. In addition, the input buffer circuit includes feedback circuitry. The feedback circuitry is configured to generate, based on the first buffered signal and the second buffered signal, a first feedback signal and a second feedback signal for mitigating a respective unwanted signal component at the first input node and the second input node related to a limited reverse isolation of the amplifier buffer. The feedback circuitry is further configured to supply the first feedback signal to the first input node and the second feedback signal to the second input node.

Methods, systems, and devices for wireless communications are described. In some cases, a device may perform a first analog to digital conversion (ADC) to generate a first set of samples of a wireless signal, and may attenuate the signal according to a dynamic range. The device may then perform a second ADC on the attenuated signal to generate a second set of samples, amplify the second set of samples, output whichever set of samples is greater. In some other cases, the second ADC may determine to attenuate the wireless signal based on an input power, amplify the signal, and output the amplified samples. In some other cases, the wireless device may determine an estimated input power of the wireless signal at a number of antenna elements. The device may then determine an adjustment to gain states of low-noise amplifiers (LNA) associated with each of the number of antenna elements.

Example embodiments relate to time-interleaved analog-to-digital converters and conversion methods thereof. One embodiment includes a slope analog-to-digital converter. The slope analog-to-digital converter includes a sample and hold stage configured to sample an analog input signal at a sampling frequency. The slope analog-to-digital converter also includes a comparator downstream to the sample and hold stage configured to compare the analog input signal to a slope signal. Further, the slope analog-to-digital converter includes a digital logic configured to receive a counter value corresponding to a voltage level of the slope signal and to sample the counter value based upon the comparison, thereby generating a digital representation of the analog input signal based upon the comparison. The slope signal is asynchronous to the sampling frequency.