An analog-to-digital converter (ADC) including: a signal input adapted to receive an analog signal; a first reference voltage input adapted to receive a first reference voltage; a second reference voltage input adapted to receive a second reference voltage, the second reference voltage is different than the first reference voltage; a first delay circuit having a first delay input coupled to the signal input, a second delay input coupled to the first reference voltage input, a first delay output and a second delay output; a second delay circuit having a third delay input coupled to the signal input, a fourth delay input coupled to the second reference voltage input; a third delay output and a fourth delay output; a first comparator having a first comparator input coupled to the first delay output, a second comparator input coupled to the second delay output and a first comparator output; and a second comparator having a third comparator input coupled to the third delay output, a fourth comparator input coupled to the fourth delay output and a second comparator output.

A segmented digital-to-analog converter (DAC) includes DAC segments, an overrange DAC, and a dither control circuit. Each DAC segment includes a plurality of DAC cells for generating an analog output signal based on input data to each DAC segment. The overrange DAC generates an analog output signal based on a control signal. The dither control circuit adds a dither to first input data supplied to a higher-order DAC segment, subtract a portion of the dither from second input data supplied to a lower-order DAC segment, and generate the control signal for subtracting a remaining portion of the dither from an output of the segmented DAC in an analog domain. The dither added to the first input data may be one of +1, 0, and −1 and the portion of the dither subtracted from the second input data may be a half of the dither added to the first input data.

Techniques for interpolating two voltages without loading them and without requiring significant power or additional area are described. The techniques include specific topologies for the buffering amplifiers that offer accuracy by cancelling systematic error sources without relying on high gain, thus simplifying the frequency compensation, and reducing power consumption. This can be achieved by biasing the amplifiers from the load current by an innovative feedback structure, which can remove the need for high impedance nodes inside the amplifiers.

An Artificial Neural Network (ANN) processing system includes artificial neurons (processing elements) and an analog to digital converter (ADC). An artificial neuron includes a digital to analog converter (DAC) and a low pass filter (LPF) configured to generate a first filtered analog current signal. Also, the artificial neuron includes a delta-sigma DAC configured to generate an M-bit current signal based on a digital weight value. The artificial neuron also includes a multiplier configured to generate a first output current source signal based on the first filtered analog current signal and the M-bit current signal. The ADC is operably coupled to a common node via a single line and configured to generate a digital output signal based on an input voltage of the ADC. The digital output signal is representative of a summation of output analog current signals at a common node to which the ADC is operably coupled.

An Artificial Neural Network (ANN) processing system includes artificial neurons (processing elements) and an analog to digital converter (ADC). An artificial neuron includes a digital to analog converter (DAC) and a low pass filter (LPF) configured to generate a first filtered analog current signal. Also, the artificial neuron includes a delta-sigma DAC configured to generate an M-bit current signal based on a digital weight value. The artificial neuron also includes a multiplier configured to generate a first output current source signal based on the first filtered analog current signal and the M-bit current signal. The ADC is operably coupled to a common node via a single line and configured to generate a digital output signal based on an input voltage of the ADC. The digital output signal is representative of a summation of output analog current signals at a common node to which the ADC is operably coupled.

Techniques for interpolating two voltages without loading them and without requiring significant power or additional area are described. The techniques include specific topologies for the buffering amplifiers that offer accuracy by cancelling systematic error sources without relying on high gain, thus simplifying the frequency compensation, and reducing power consumption. This can be achieved by biasing the amplifiers from the load current by an innovative feedback structure, which can remove the need for high impedance nodes inside the amplifiers.

A single-ended analog signal receiver apparatus is provided, which can cope with an external ground current and an undefined impedance through an AC bootstrap input impedance, while considering electromagnetic compatibility, convert a received single-ended analog signal into a balanced output differential signal, and may provide at a post-stage circuit output an output signal with lower noise through common mode rejection.

Mechanisms for reducing or eliminating a quantization error caused by a quantizer of a continuous-time (CT) residue generation system are disclosed. In particular, systems and methods described herein are based on using a dither generation and injection circuit that can perform a high-pass filtering of the additive dither signal (i.e., a high-pass shaped dither signal). Using high-pass shaped dither signals is expected to improve quantizer linearity without significantly reducing the available error correction range. The applied dither may be particularly effective at minimizing signal-dependent distortion in ADC output spectrum caused by the quantizer when the quantization error cancellation accuracy may be insufficient.

Methods and devices for digitizing an analog repetitive signal using waveform averaging are described. An example method includes generating a discrete set of analog dither offset voltages, wherein at least two of the discrete set of analog dither offset voltages are different from each other, receiving the analog repetitive signal comprising multiple instances of a waveform, wherein the waveform has a waveform duration, generate a timing alignment to align each waveform of the analog repetitive signal and the corresponding analog dither offset voltage over the waveform duration, combining, based on the timing alignment, each waveform and the corresponding analog dither offset voltage over the waveform duration to produce an analog output signal, converting the analog output signal to a digital output signal, and producing, based on the timing alignment, a digital averaged signal based on averaging the multiple instances of the waveform in the analog output signal.

A SAR ADC and an electronic device are disclosed. The SAR ADC includes a read clock generation circuit, configured to connect to a first output terminal and a second output terminal of a dynamic comparator, and generate a read clock signal for reading a first or a second comparison result based on the first and the second comparison result received from the dynamic comparator. The invention reads the comparison result using the read clock signal generated by grabbing the output of the comparator, and can improve the overall analog-to-digital conversion speed of the SAR ADC. Further, the present invention can detect the occurrence of metastable state of the comparator by judging that the output of the comparator has no pulse, and read the comparison result based on the backup clock generated by the operating clock of the comparator.