An encoder system includes a configurable detector array, wherein the configurable detector array includes a plurality of detectors. In an embodiment, the encoder system includes an application-specific integrated circuit (ASIC). The encoder system may also include a memory operable to store a partition map that defines a state for each of the plurality of detectors. In an embodiment, the memory includes a non-volatile memory. The encoder system may also include a controller, such as a microcontroller, operable to read from the memory the partition map and to adjust the partition map according to a misalignment measurement before configuring the configurable detector array. The encoder system may also include an emitter operable to generate a flux modulated by a motion object, wherein the configurable detector array is operable to receive the flux and generate respective current outputs for each of the detectors in response to the flux.

The present disclosure may be embodied as an optical encoder system comprising a first optical sensor, a second optical sensor, a first up-down counter, a second up-down counter, and an I/O expander. The optical encoder system may further include a buffer. The present disclosure may also be embodied as an optical encoder system comprising an optical encoder, and a monostable multivibrator. The present disclosure may also be embodied as a method for encoding optical data comprising generating a first optical sensor signal and a second optical sensor signal, converting the first optical sensor signal and second optical sensor signal into four first counter signals, generating a borrow output signal and a carry output signal, converting the borrow output signal and the carry output signal into four second counter signals, and converting the first counter signals and second counter signals into a serial data signal and a serial clock signal.

An encoder system includes a configurable detector array, wherein the configurable detector array includes a plurality of detectors. The encoder system may also include a memory operable to store a partition map that defines a state for each of the plurality of detectors. The encoder system may also include an emitter operable to generate a flux modulated by a motion object, wherein the configurable detector array is operable to receive the flux and generate respective current outputs for each of the detectors in response to the flux. In an embodiment, the current outputs from detectors having a same state are grouped together. The encoder system may also include one or more current duplicators to duplicate the current outputs from detectors having one state to group with the current outputs from detectors having a different state. The encoder system may also adjust weights of the current outputs.

An encoder system includes a configurable detector array, wherein the configurable detector array includes a plurality of detectors. In an embodiment, the encoder system includes an application-specific integrated circuit (ASIC). The encoder system may also include a memory operable to store a partition map that defines a state for each of the plurality of detectors. In an embodiment, the memory includes a non-volatile memory. The encoder system may also include a controller, such as a microcontroller, operable to read from the memory the partition map and to adjust the partition map according to a misalignment measurement before configuring the configurable detector array. The encoder system may also include an emitter operable to generate a flux modulated by a motion object, wherein the configurable detector array is operable to receive the flux and generate respective current outputs for each of the detectors in response to the flux.

The present disclosure may be embodied as an optical encoder system comprising a first optical sensor, a second optical sensor, a first up-down counter, a second up-down counter, and an I/O expander. The optical encoder system may further include a buffer. The present disclosure may also be embodied as an optical encoder system comprising an optical encoder, and a monostable multivibrator. The present disclosure may also be embodied as a method for encoding optical data comprising generating a first optical sensor signal and a second optical sensor signal, converting the first optical sensor signal and second optical sensor signal into four first counter signals, generating a borrow output signal and a carry output signal, converting the borrow output signal and the carry output signal into four second counter signals, and converting the first counter signals and second counter signals into a serial data signal and a serial clock signal.

A key control device and a key control method are disclosed. The key control device includes: an encoder circuit including a first output terminal and a second output terminal and configured to output a first voltage signal and a second voltage signal through the first output terminal and the second output terminal respectively, under triggering of a rotational operation; a first interface extension circuit configured to receive the first voltage signal and the second voltage signal, and generate an interrupt signal and voltage state transition data in response to the first voltage signal or the second voltage signal output by the encoder circuit; and a main control circuit configured to determine a rotation direction of the rotation operation according to the interrupt signal and the voltage state transition data.

One or more embodiments are directed to an encoder configured to output a signal, and a computing device configured to receive the signal from the encoder and generate a reduced resolution version of the signal, the computing device is configured to transmit the reduced resolution version of the signal to a recipient.

An integrated circuit includes a set of N unit analog-to-digital converters (ADCs) having a common architecture, and which provide an aggregate data rate. Moreover, the integrated circuit includes control logic that selects subsets of the set of N unit ADCs in order to realize sub-ADCs of different data rates that can each be an arbitrary integer multiple of an inverse of N times the aggregate data rate of the N unit ADCs. Furthermore, the control logic may dynamically select the subsets on the fly or on a frame-by-frame basis. This dynamically selection may occur at boot time and/or a runtime. Additionally, the given different data rate may correspond to one or more phases of a multi-phase clock in the integrated circuit, where the multiphase clock may include a number of phases corresponding to a number of possible subsets, and given selected subsets may not use all of the available phases.

An analog-to-digital converter ADC includes a first successive approximation register analog-to-digital converter (SAR ADC) configured to convert an in-phase input signal to digital data using a first integrator, a second successive approximation register analog-to-digital converter (SAR ADC) configured to convert a quadrature input signal to digital data using a second integrator, and first to fourth sampling capacitors configured to transmit an output of the first integrator to an input terminal of the second integrator, and transmit an output of the second integrator to an input terminal of the first integrator when the first integrator and the second integrator integrate the sampled in-phase input signal and the quadrature input signal, respectively. The first and second SAR ADCs and the first to fourth sampling capacitors are driven according to an operation sequence of a sampling stage, a conversion stage, and an integration stage.

An integrated circuit includes a set of N unit analog-to-digital converters (ADCs) having a common architecture, and which provide an aggregate data rate. Moreover, the integrated circuit includes control logic that selects subsets of the set of N unit ADCs in order to realize sub-ADCs of different data rates that can each be an arbitrary integer multiple of an inverse of N times the aggregate data rate of the N unit ADCs. Furthermore, the control logic may dynamically select the subsets on the fly or on a frame-by-frame basis. This dynamically selection may occur at boot time and/or a runtime. Additionally, the given different data rate may correspond to one or more phases of a multi-phase clock in the integrated circuit, where the multiphase clock may include a number of phases corresponding to a number of possible subsets, and given selected subsets may not use all of the available phases.