A semiconductor integrated circuit includes a converter converting an analog signal into a digital signal based on a clock signal; a comparator determining values of data based on the digital signal; a recovery circuit recovering the clock signal based on the digital signal and the data; and a control circuit. The recovery circuit includes a phase detector calculating a sum of a first value and offset, the first value being a value based on the digital signal and the data and relating to a phase of the clock signal; and a loop filter calculating a correction amount of the phase of the clock signal based on the sum. The control circuit is configured to gradually change the offset from a second value to zero after the second value is added as the offset.

A semiconductor integrated circuit includes a converter converting an analog signal into a digital signal based on a clock signal; a comparator determining values of data based on the digital signal; a recovery circuit recovering the clock signal based on the digital signal and the data; and a control circuit. The recovery circuit includes a phase detector calculating a sum of a first value and offset, the first value being a value based on the digital signal and the data and relating to a phase of the clock signal; and a loop filter calculating a correction amount of the phase of the clock signal based on the sum. The control circuit is configured to gradually change the offset from a second value to zero after the second value is added as the offset.

In a first sensitivity level, an AD converter performs AD conversion selectively using, in accordance with the level of the analog signal, any one of a first reference signal and a second reference signal that have mutually different slopes, and in a second sensitivity level that is different from the first sensitivity level, the AD converter performs AD conversion only using a third reference signal.

In a first sensitivity level, an AD converter performs AD conversion selectively using, in accordance with the level of the analog signal, any one of a first reference signal and a second reference signal that have mutually different slopes, and in a second sensitivity level that is different from the first sensitivity level, the AD converter performs AD conversion only using a third reference signal.

A high resolution analog to digital converter (ADC) with improved bandwidth senses an analog signal (e.g., a load current) to generate a digital signal. The ADC operates based on a load voltage produced based on charging of an element (e.g., a capacitor) by a load current and a digital to analog converter (DAC) output current (e.g., from a N-bit DAC). The ADC generates a digital output signal representative of a difference between the load voltage and a reference voltage. This digital output signal is used directly, or after digital signal processing, to operate an N-bit DAC to generate a DAC output current that tracks the load current. In addition, quantization noise is subtracted from the digital output signal thereby extending the operational bandwidth of the ADC. In certain examples, the operational bandwidth of the ADC extends up to 100s of kHz (e.g., 200-300 kHz), or even higher.

A high resolution analog to digital converter (ADC) with improved bandwidth senses an analog signal (e.g., a load current) to generate a digital signal. The ADC operates based on a load voltage produced based on charging of an element (e.g., a capacitor) by a load current and a digital to analog converter (DAC) output current (e.g., from a N-bit DAC). The ADC generates a digital output signal representative of a difference between the load voltage and a reference voltage. This digital output signal is used directly, or after digital signal processing, to operate an N-bit DAC to generate a DAC output current that tracks the load current. In addition, quantization noise is subtracted from the digital output signal thereby extending the operational bandwidth of the ADC. In certain examples, the operational bandwidth of the ADC extends up to 100s of kHz (e.g., 200-300 kHz), or even higher.

An AD converter includes: an integration unit 22 that uses an input voltage as an initial value and repeats an operation of integrating one or both of two types of unit voltages with the input voltage, thereby generating an integrated voltage; a switching threshold voltage unit 23 that includes two types of threshold voltages causing the operation of integrating to be terminated; a comparator 24 that compares the integrated voltage with the threshold voltages; an integration determination unit 11 that, before the operation of integrating is started, causes the comparator 24 to compare the input voltage with a rough adjustment threshold voltage corresponding to a larger one of the unit voltages; a unit voltage switching control unit 12 that, when the rough adjustment threshold voltage is larger than the input voltage, controls the integration unit 22 to generate the integrated voltage by using the two types of unit voltages; and a single unit voltage control unit 13 that, when the rough adjustment threshold voltage is smaller than the input voltage, controls the integration unit 22 to generate the integrated voltage by using only a smaller one of the unit voltages.

An AD converter includes: an integration unit 22 that uses an input voltage as an initial value and repeats an operation of integrating one or both of two types of unit voltages with the input voltage, thereby generating an integrated voltage; a switching threshold voltage unit 23 that includes two types of threshold voltages causing the operation of integrating to be terminated; a comparator 24 that compares the integrated voltage with the threshold voltages; an integration determination unit 11 that, before the operation of integrating is started, causes the comparator 24 to compare the input voltage with a rough adjustment threshold voltage corresponding to a larger one of the unit voltages; a unit voltage switching control unit 12 that, when the rough adjustment threshold voltage is larger than the input voltage, controls the integration unit 22 to generate the integrated voltage by using the two types of unit voltages; and a single unit voltage control unit 13 that, when the rough adjustment threshold voltage is smaller than the input voltage, controls the integration unit 22 to generate the integrated voltage by using only a smaller one of the unit voltages.

Herein disclosed are some examples of metastability detectors and compensator circuitry for successive-approximation-register (SAR) analog-to-digital converters (ADCs) within delta sigma modulator (DSM) loops. A metastability detector may detect metastability at an output of a SAR ADC and compensator circuitry may implement a compensation scheme to compensate for the metastability. The identification of the metastability and/or compensation for the metastability can avoid detrimental effects and/or errors to the DSM loops that may be caused by the metastability of the SAR ADCS.

According to one embodiment, in a semiconductor integrated circuit, the plurality of storage devices are arranged in a form of a plurality of rows. Each of the storage devices are configured to store a bit position value of a weight of multiple bits. The plurality of multiplication circuits are arranged in a form of a plurality of rows and are configured to multiply a plurality of input voltages by the weight of multiple bits to generate a plurality of multiplication results. The one or more capacitive devices are configured to accumulate charges corresponding to the plurality of multiplication results. The adder circuit are configured to generate an output voltage corresponding to the total value of the charges accumulated in the one or more capacitive devices. The plurality of input voltages have different amplitudes. Each of the input voltages is associated with a corresponding bit position of the weight.