An analog-to-digital converter includes: a voltage-current converter receiving an analog input voltage, generating a first digital signal from the analog input voltage, and outputting a residual current remaining after the first digital signal; a current-time converter converting the residual current into a current time in a time domain; and a time-digital converter receiving the residual time, and generating a second digital signal from the residual time, wherein the first digital signal and the second digital signal are sequences of digital codes representing respective signal levels of the analog input voltage.

Systems and methods for interrogating sensing systems utilising bursts of samples. Bursts of samples correspond to optical pulses returning from optical sensors, where pulses are spaced at a period significantly longer than the pulse width, giving irregular sample spacing. The interrogation system and method processes the irregular busts of samples to recover phase information from received signals.

Certain aspects of the present disclosure provide a digital-to-analog converter (DAC) system. The DAC system generally includes a plurality of current steering cells, each comprising a current source coupled to at least two current steering switches, wherein control inputs of the at least two current steering switches are coupled to an input path of the DAC system. The DAC system may also include a current source toggle circuit configured to selectively disable the current source of at least one of the plurality of current steering cells, and a feedforward path coupled between the input path and at least one control input of the current source toggle circuit.

In an analog-to-digital converter, primary latches respectively latch an output of a corresponding one of delay units at respective sample times of different first clocks. The primary latches include at least first and second primary latches, and secondary latches include at least first and second secondary latches respectively corresponding to the at least first and second primary latches. Each of the at least first and second secondary latches is configured to latch, at a sample time of a common second clock, an output of a corresponding one of the at least first and second primary latches. The common second clock is based on at least one of the first clocks.

In an example, a system includes an input channel and a voltage to delay converter (V2D) coupled to the input channel. The system also includes a first multiplexer coupled to the V2D and an analog-to-digital converter (ADC) coupled to the first multiplexer. The system includes a second multiplexer coupled to the input channel and an auxiliary ADC coupled to the second multiplexer. The system includes calibration circuitry coupled to an output of the auxiliary ADC, where the calibration circuitry is configured to correct a non-linearity in a signal provided by the input channel. The calibration circuitry is also configured to determine the non-linearity of the signal provided to the ADC relative to the signal provided to the auxiliary ADC.

In an analog-to-digital converter circuit, a sum output unit calculates the sum of an n-bit data value outputted from a first output unit and an (n + 1)-bit data value outputted from a second output unit to accordingly obtain the calculated sum as a digital data value. A second calculator of the second output unit calculates the sum of a sign bit of a third digital data value as a most significant bit thereof and a second significant bit of the third digital data value. The combines a bit selected from the calculated sum with the third digital data value from which the sign bit has been eliminated to accordingly generate, as the (n + 1)-bit data value, a new digital data value whose most significant bit is the bit selected from the calculated sum.

In an A/D converter circuit, time required for a first pulse signal to have passed through all first delay units of a first pulse delay circuit is defined as first turnaround time, and time required for a second pulse signal to have passed through all second delay units of a second pulse delay circuit is defined as second turnaround time. Average time required for the first pulse signal to pass through any of the first delay units is defined as first passage time, and average time required for the second pulse signal to pass through any of the second delay units is defined as second passage time. A difference between the first and second passage times enables a difference between the first and second turnaround times to be smaller as compared with a reference difference therebetween for a case where the first and second passage times are identical to each other.

A time-to-digital converter including N stages of converting circuits, where N≧2, and N is an integer. Each stage of converting circuit includes a first delayer and an arbiter; an output end of the first delayer in each stage of converting circuit outputs a delayed signal of the stage of converting circuit; and the arbiter in each stage of converting circuit receives a sampling clock and the delayed signal of the stage of converting circuit, and compares the sampling clock with the delayed signal to obtain an output signal of the stage of converting circuit. Output signals of the N stages of converting circuits form a non-linear binary number, to indicate a time difference between a clock signal and a reference signal.

A two-stage successive-approximation-register (SAR) analog-to-digital converter (ADC) comprising is described. The SAR ADC includes a first stage comprising a SAR ADC; a voltage-to-time interface that translates a voltage-domain residue from the SAR ADC to a time-domain residue; and a second stage comprising a time-to-digital converter (TDC) that resolves multiple bits from the time-domain residue.

An LDO regulator includes a voltage-to-time converter configured to convert a fluctuation in an output voltage sensed from an output node into a time domain signal having a pulse type, and output the time domain signal, based on a clock signal; a time-to-voltage converter configured to receive the time domain signal, convert the time domain signal into a first voltage control signal performing first compensation for the output voltage, and output the first voltage control signal; an analog amplifier configured to output a second voltage control signal continuously performing second compensation for the output voltage, regardless of the clock signal; and a first pass transistor configured to drive the output voltage based on the second voltage control signal. The LDO regulator is configured to reduce the fluctuation in the output voltage, based on the first compensation and the second compensation.