An auto calibration method used in switching converters with constant on-time control. The auto calibration method includes: generating a periodical clock signal with a predetermined duty cycle; providing a first voltage and a second voltage to an on-time control circuit to generate an on-time control signal based on the first and second voltage; providing the clock signal and on-time control signal to a logic circuit to generate a switch control signal based on the clock signal and on-time control signal; comparing the duty cycle of the switch control signal with the duty cycle of the clock signal to adjust a calibration code signal; and adjusting circuit parameters of the on-time control circuit in accordance with the calibration code signal.

An auto calibration method used in switching converters with constant on-time control. The auto calibration method includes: generating a periodical clock signal with a predetermined duty cycle; providing a first voltage and a second voltage to an on-time control circuit to generate an on-time control signal based on the first and second voltage; providing the clock signal and on-time control signal to a logic circuit to generate a switch control signal based on the clock signal and on-time control signal; comparing the duty cycle of the switch control signal with the duty cycle of the clock signal to adjust a calibration code signal; and adjusting circuit parameters of the on-time control circuit in accordance with the calibration code signal.

An AD converter includes: an integration unit 22 that uses an input voltage as an initial value and repeats an operation of integrating one or both of two types of unit voltages with the input voltage, thereby generating an integrated voltage; a switching threshold voltage unit 23 that includes two types of threshold voltages causing the operation of integrating to be terminated; a comparator 24 that compares the integrated voltage with the threshold voltages; an integration determination unit 11 that, before the operation of integrating is started, causes the comparator 24 to compare the input voltage with a rough adjustment threshold voltage corresponding to a larger one of the unit voltages; a unit voltage switching control unit 12 that, when the rough adjustment threshold voltage is larger than the input voltage, controls the integration unit 22 to generate the integrated voltage by using the two types of unit voltages; and a single unit voltage control unit 13 that, when the rough adjustment threshold voltage is smaller than the input voltage, controls the integration unit 22 to generate the integrated voltage by using only a smaller one of the unit voltages.

A method includes receiving analog body-surface signal from body-surface electrode, and multiple analog unipolar signals from multiple unipolar electrodes of an invasive probe. A first unipolar electrode is assigned to serve as a common electrical ground and a common timing reference for the analog unipolar signals and the analog body-surface signal. The analog unipolar signals are digitized to produce digital unipolar signals sampled relative to a digital ground. Defined are an analog bipolar signal between the first unipolar electrode and a second unipolar electrode of the probe, and digital bipolar signal formed from the first unipolar electrode and the second unipolar electrode. Ground and timing offsets between the analog bipolar signal and the digital bipolar signal are estimated, while the first unipolar electrode is connected to the digital ground. The ground offset and the timing offset are applied in measuring a third unipolar signal, sensed by a third unipolar electrode.

A method includes receiving analog body-surface signal from body-surface electrode, and multiple analog unipolar signals from multiple unipolar electrodes of an invasive probe. A first unipolar electrode is assigned to serve as a common electrical ground and a common timing reference for the analog unipolar signals and the analog body-surface signal. The analog unipolar signals are digitized to produce digital unipolar signals sampled relative to a digital ground. Defined are an analog bipolar signal between the first unipolar electrode and a second unipolar electrode of the probe, and digital bipolar signal formed from the first unipolar electrode and the second unipolar electrode. Ground and timing offsets between the analog bipolar signal and the digital bipolar signal are estimated, while the first unipolar electrode is connected to the digital ground. The ground offset and the timing offset are applied in measuring a third unipolar signal, sensed by a third unipolar electrode.

An analog-to-digital converter, ADC, circuitry, comprises: an integrator connected to a capacitor, the integrator being configured to switch between integrating an analog input signal for ramping an integrator output and integrating a reference input signal for returning integrator output towards a threshold; a comparator for comparing integrator output to the threshold; and a timer for determining a time duration during which the reference input signal is integrated, the time duration providing a digital representation of an analog input signal value; the ADC circuitry further comprising a feedforward noise shaping loop configured to store a quantization error signal based on digitizing a first sample, the comparator being configured to receive a feedforward noise shaping signal for changing the threshold for digitizing a later sample of the analog input signal following the first sample.

Various embodiments of the present technology may comprise methods and apparatus for a multi-cycle time-based ADC configured to convert an analog signal to a digital value. Methods and apparatus a multi-cycle time-based ADC according to various aspects of the present invention may comprise a plurality of VTCs configured to perform multiple voltage-to-time conversions out-of-phase from each other. The integration times for each VTC may be summed to provide a total integration time, which may then be converted to the digital value.

A voltage-mode integrate-and-dump photonic ADC front-end circuit includes a current integrator for immediately integrating current pulses onto a capacitor voltage, the current pulses converted by photodetectors from optical data pulses corresponding to a received analog input signal. The circuit may include dampeners for reducing voltage ringing and resulting intersymbol interference (ISI) to preserve SNR at high data rates. The integrating capacitor may be discharged by a reset switch based on clock signals generated by a master clock; the reset switch may include a pulse width controller enabling the integrating capacitor to track and hold the integrated voltage, rather than downstream sample-and-hold amplifiers. Quantizers and other signal processors generate digital signal output by sampling and digitizing the integrated voltage output of the current integrator.

An integrated circuit includes an analog-to-digital converter (ADC) configured to receive input voltage, and first and second reference voltages, and outputs digital code representing ratios between the input voltage and the first and the second reference voltages. The first and second reference voltages are generated by a reference generator using different current densities. During a first stage, the ADC samples the first input voltage and the first reference voltage and transfers equivalent charge of the sampled first input voltage and first reference voltage to an integration capacitor. During a second stage, the ADC samples the second reference voltage and transfers equivalent charge of the sampled second reference voltage to the integration capacitor. The ADC provides one bit of digital code based on total charge stored on the integration capacitor after the transfers of charge of the sampled input voltage, and the sampled first and second reference voltages.

An analog-to-digital converter may include an integrator, a gated ring oscillator, a coarse counter, a phase state register, a counter register, and logic circuitry. The gated ring oscillator may output a phase state signal continuously to the phase state register. The phase state signal includes multiple phase nodes, each of which is created by transmitting a signal through a number of delay stages. One of the phase nodes may be provided to the coarse counter. The phase state register and counter register may store the most current corresponding phase state and coarse counter outputs, respectively. A control signal corresponding to an analog image input signal may control the output of stored phase states and stored coarse counter outputs to the logic circuitry. The logic circuitry may generate a digital version of the analog image input signal based on the outputs of the phase state and counter registers.