An AD converter with self-calibration function that does not require an instrument for calibration, and includes: a reference voltage unit that generates a reference voltage; a summation and conversion unit that has two or more unit voltages serving as units of amount of change in a summed voltage, and during conversion, sums up any one unit voltage of the two or more unit voltages until the summed voltage exceeds the reference voltage, with an input voltage being an initial value of the summed voltage; and a control unit including a calibration control section that calibrates the two or more unit voltages and an offset voltage of a comparator at a time of calibration, and a conversion control section that determines a polarity of the offset voltage of the comparator and thereafter converts the input voltage to a digital value during conversion.

A digital-to-analog converter system has digital-to-analog converters, a common output, and a digital controller for transmitting first codes to one of the converters at a radio-frequency digital rate, and for transmitting second codes to another one of the converters at the same rate. The digital controller includes a timing system for operating each converter at the digital rate in a return-to-zero configuration, such that a signal from the first converter is transmitted to the common output while the second converter is reset, and vice versa. The digital-to-analog converter system can generate a radio-frequency analog signal having signals in first and second Nyquist zones simultaneously.

A digital-to-analog converter system has digital-to-analog converters, a common output, and a digital controller for transmitting first codes to one of the converters at a radio-frequency digital rate, and for transmitting second codes to another one of the converters at the same rate. The digital controller includes a timing system for operating each converter at the digital rate in a return-to-zero configuration, such that a signal from the first converter is transmitted to the common output while the second converter is reset, and vice versa. The digital-to-analog converter system can generate a radio-frequency analog signal having signals in first and second Nyquist zones simultaneously.

An apparatus is disclosed for pipelined analog-to-digital conversion. In an example aspect, the apparatus includes a pipelined analog-to-digital converter (ADC). The pipelined ADC includes a first stage and a second stage. The first stage includes a sampler and a quantizer coupled to the sampler. The first stage also includes a current distribution circuit coupled to the sampler. The second stage includes a sampler coupled to the current distribution circuit and a quantizer coupled to the sampler of the second stage.

The present technology relates to a measurement circuit, a driving method, and an electronic instrument capable of reducing power consumption. In the measurement circuit, irradiation light is emitted from the light emitting unit toward the object, and light from the object is received to measure pulse waves or the like. The measurement circuit includes: a light receiving unit that receives light from an object; an integrating unit that performs integration of a current generated in accordance with the reception of the light by the light receiving unit and generates a voltage according to the amount of reception of the light; and a pulse generating unit that generates a pulse signal having a pulse width corresponding to the amount of reception of the light on the basis of the voltage. The present technology can be applied to electronic instruments such as wearable devices, for example.

An analog-to-digital converter, ADC, circuitry, comprises: an integrator connected to a capacitor, the integrator being configured to switch between integrating an analog input signal for ramping an integrator output and integrating a reference input signal for returning integrator output towards a threshold; a comparator for comparing integrator output to the threshold; and a timer for determining a time duration during which the reference input signal is integrated, the time duration providing a digital representation of an analog input signal value; the ADC circuitry further comprising a feedforward noise shaping loop configured to store a quantization error signal based on digitizing a first sample, the comparator being configured to receive a feedforward noise shaping signal for changing the threshold for digitizing a later sample of the analog input signal following the first sample.

A hybrid analog-to-digital converter (ADC) includes a plurality of analog-to-digital conversion circuits and a combining circuit. The analog-to-digital conversion circuits generate a plurality of partial digital outputs for a same analog input, respectively, wherein the analog-to-digital conversion circuits include a digital slope ADC used to perform signal quantization in a time domain. The combining circuit combines the partial digital outputs generated from the analog-to-digital conversion circuits to generate a final digital output of the analog input.

A hybrid analog-to-digital converter (ADC) includes a plurality of analog-to-digital conversion circuits and a combining circuit. The analog-to-digital conversion circuits generate a plurality of partial digital outputs for a same analog input, respectively, wherein the analog-to-digital conversion circuits include a digital slope ADC used to perform signal quantization in a time domain. The combining circuit combines the partial digital outputs generated from the analog-to-digital conversion circuits to generate a final digital output of the analog input.

Certain aspects of the present disclosure provide a successive approximation register (SAR) analog-to-digital converter (ADC) implemented with a digital filter for noise shaping. For example, certain aspects provide a circuit for analog-to-digital conversion having: a first digital-to-analog converter (DAC) having an output coupled to a sampling node; a comparator having an input coupled to the sampling node; SAR logic having an input coupled to an output of the comparator and at least one output coupled to an input of the first DAC; a quantizer configured to generate a first digital signal representing a voltage at the sampling node; a digital filter configured to apply a filter to the first digital signal; and a second DAC configured to generate an analog signal representing the filtered first digital signal and provide the analog signal to the sampling node.

Techniques are described for implementing ramp voltage generators with current steering architectures that provide high power supply noise rejection. For example, a current steering architecture uses a sample and hold block and a driver block to control and drive a current steering network. Both generate signals that track supply voltage variations, and those signals are used to generate a ramp voltage. For image sensor applications, image tolerance to ramp noise can be very low when the ramp voltage is low, but can increase appreciably as the ramp voltage increases. As such, embodiments can be implemented to provide high PSR at low ramp voltages, even if the PSR degrades at higher ramp voltages, while maintaining high linearity over the entire ramp voltage.