A switched-capacitor amplifier comprises a comparator, sample and amplification capacitors and a controller to control charge and discharge current sources in dependence on an output signal of the comparator. A closed loop control circuit is configured to determine the delay of the comparator and control an offset of the comparator in response to the determined delay.

A ramp generator providing ramp signal with high resolution fine gain includes a current mirror having a first and second paths to conduct a capacitor current and an integrator current responsive to the capacitor current. First and second switched capacitor circuits are coupled to the first path. A fractional divider circuit is coupled to receive a clock signal to generate in response to an adjustable fractional divider ratio K a switched capacitor control signal that oscillates between first and second states to control the first and second switched capacitor circuits. The first and second switched capacitor circuits are coupled to be alternatingly charged by the capacitor current and discharged in response to each the switched capacitor control signal. An integrator coupled is to the second path to generate the ramp signal in response to the integrator current.

A ramp generator providing ramp signal with high resolution fine gain includes a current mirror having a first and second paths to conduct a capacitor current and an integrator current responsive to the capacitor current. First and second switched capacitor circuits are coupled to the first path. A fractional divider circuit is coupled to receive a clock signal to generate in response to an adjustable fractional divider ratio K a switched capacitor control signal that oscillates between first and second states to control the first and second switched capacitor circuits. The first and second switched capacitor circuits are coupled to be alternatingly charged by the capacitor current and discharged in response to each the switched capacitor control signal. An integrator coupled is to the second path to generate the ramp signal in response to the integrator current.

In a first sensitivity level, an AD converter performs AD conversion selectively using, in accordance with the level of the analog signal, any one of a first reference signal and a second reference signal that have mutually different slopes, and in a second sensitivity level that is different from the first sensitivity level, the AD converter performs AD conversion only using a third reference signal.

The present disclosure relates to a comparator, an AD converter, a solid-state image pickup device, an electronic device, a method of controlling the comparator, a data writing circuit, a data reading circuit, and a data transferring circuit, capable of improving the determining speed of the comparator and reducing power consumption. The comparator includes: a differential input circuit configured to operate with a first power supply voltage, the differential input circuit configured to output a signal when an input signal is higher than a reference signal in voltage; a positive feedback circuit configured to operate with a second power supply voltage lower than the first power supply voltage, the positive feedback circuit being configured to accelerate transition speed when a compared result signal indicating a compared result between the input signal and the reference signal in voltage, is inverted, on the basis of the output signal of the differential input circuit; and a voltage conversion circuit configured to convert the output signal of the differential input circuit into a signal corresponding to the second power supply voltage. The present disclosure can be applied to, for example, a comparator of a solid-state image pickup device.

An apparatus is disclosed for analog-to-digital conversion. In an example aspect, the apparatus includes an analog-to-digital converter (ADC). The ADC includes a reference-crossing detector having an input and an output. The ADC also includes a ramp generator coupled between the output of the reference-crossing detector and the input of the reference-crossing detector. The ADC further includes a voltage shifter coupled between the output of the reference-crossing detector and the input of the reference-crossing detector.

A photodetection device according to the present disclosure includes: a pixel; a reference signal generation unit; a comparison circuit; and a first switch. The pixel is configured to generate a pixel signal. The reference signal generation unit is configured to generate a reference signal. The comparison circuit includes a first-stage amplifier circuit and a second-stage amplifier circuit that is coupled to the first-stage amplifier circuit through a connection node. The first-stage amplifier circuit is configured to output a first output signal corresponding to a comparison operation based on the pixel signal and the reference signal. The second-stage amplifier circuit is configured to output a second output signal corresponding to the first output signal outputted from the first-stage amplifier circuit through the connection node. The first switch has one end and another end. The one end is coupled to the connection node. The first switch allows impedance and a voltage at the connection node to change.

A light receiving unit receives a pulsed optical signal arriving from a search region. A branching unit generates, from a received light signal, a plurality of branch signals having signal intensities proportional to a signal intensity of the received light signal and different from one another. A conversion unit converts, from analog to digital, a signal fed via the individual path selected by a selection unit, and in accordance with a result of the conversion, a processing unit generates information regarding an object reflecting the optical signal. A control unit causes the selection unit to select one of the individual paths for which a determination unit determines that a magnitude of the fed signal is within an input range of the conversion unit and which provides the highest gain.

In a solid-state imaging element that performs AD conversion for each pixel, image quality degradation when resolution is lowered is suppressed without wastefully consuming power. The solid-state imaging element includes a plurality of pixels. Each of the plurality of pixels is provided with a comparison unit, an addition circuit, and a data storage unit. The comparison unit generates a difference signal obtained by amplifying a difference between an analog pixel signal to which a predetermined coordinate is assigned and a predetermined reference signal. The addition circuit generates an addition signal by performing analog addition of the difference signal and a difference signal regarding another coordinate adjacent to the predetermined coordinate. The data storage unit holds a digital signal indicating a time when an output signal of the comparison unit corresponding to the addition signal is inverted.

An A/D conversion circuit includes a comparison-reference-signal generator section configured to generate a comparison reference signal synchronized with a sampling clock signal, a comparator configured to compare a voltage of an input signal and a voltage of the comparison reference signal to thereby generate a trigger signal, a time to digital converter configured to calculate a first time digital value, and a digital-signal generator section configured to generate, based on the first time digital value and a second time digital value, a digital signal corresponding to the voltage of the input signal. The first time to digital converter includes a state transition section configured to start transition of a state based on the trigger signal and output state information, and a weight operation section configured to, in synchronization with the reference clock signal, perform, on a value based on the state information, weighting corresponding to time elapsing and perform a predetermined arithmetic operation to thereby calculate the first time digital value corresponding to the number of transition times of the state.