An analog to digital converter (ADC) receives first and second analog input signals. A charge sampling demultiplexer includes multiple capacitors that sample the first and second analog input signals, and generates multiple input samples representative of charge stored on the capacitors. A plurality of sub-ADCs each include first and second charge-to-time converters, which receive from the charge sampling demultiplexer respective first and second input sample of the first and second analog input signals and output respective first and second pulse-width-modulated (PWM) signals responsively to the respective first and second input samples. Temporal processing circuitry processes the PWM signals to generate a digital value indicative of a temporal difference between the first and second PWM signals. Output reordering circuitry receives the digital value from each of the sub-ADCs and generates a digital output indicative of a difference between the first and second analog input signals.

An analog to digital converter (ADC) receives first and second analog input signals. A charge sampling demultiplexer includes multiple capacitors that sample the first and second analog input signals, and generates multiple input samples representative of charge stored on the capacitors. A plurality of sub-ADCs each include first and second charge-to-time converters, which receive from the charge sampling demultiplexer respective first and second input sample of the first and second analog input signals and output respective first and second pulse-width-modulated (PWM) signals responsively to the respective first and second input samples. Temporal processing circuitry processes the PWM signals to generate a digital value indicative of a temporal difference between the first and second PWM signals. Output reordering circuitry receives the digital value from each of the sub-ADCs and generates a digital output indicative of a difference between the first and second analog input signals.

Various embodiments of the present technology may comprise methods and apparatus for a multi-cycle time-based ADC configured to convert an analog signal to a digital value. Methods and apparatus a multi-cycle time-based ADC according to various aspects of the present invention may comprise a plurality of VTCs configured to perform multiple voltage-to-time conversions out-of-phase from each other. The integration times for each VTC may be summed to provide a total integration time, which may then be converted to the digital value.

An analog signal is accurately converted into a digital signal. An oscillator generates an oscillation signal having a cycle that depends on a signal level of an input analog signal. A current bit generation unit generates, as a current bit, a bit indicating a value of the oscillation signal at each of a plurality of timings within the cycle. A delay unit delays each current bit over a predetermined period and supplies the delayed current bit as a delayed bit. A determination unit determines whether a change amount of a phase of the oscillation signal changed within the predetermined period is greater than a half cycle of the cycle. An output unit generates and outputs data indicating a period in which respective values of the current bit and the delayed bit form a specific combination when the change amount is not greater than the half cycle, and generates and outputs data indicating a period in which the respective values of the current bit and the delayed bit are the same or form the specific combination when the change amount is greater than the half cycle.

An analog to digital converter is provided. The analog to digital converter includes: an arithmetic operator combining an analog input signal with a feedback signal; a loop filter filtering an output signal of the arithmetic operator; a quantizer quantizing an output signal of the loop filter to output a digital signal; and a feedback converting the digital signal to output a feedback signal, in which the quantizer includes: a plurality of VCOs each receiving a positive output signal and a negative output signal of the loop filter and outputting VCO signals; a plurality of samplers receiving the VCO signals output from the plurality of VCOs, respectively and outputting sampled signals; and a phase detector detecting a phase difference in the sampled signals output from the plurality of samplers, respectively, to detect a phase difference in two VCO signals output from the plurality of VCOs, respectively.

Certain aspects of the present disclosure provide a successive approximation register (SAR) analog-to-digital converter (ADC) implemented with a digital filter for noise shaping. For example, certain aspects provide a circuit for analog-to-digital conversion having: a first digital-to-analog converter (DAC) having an output coupled to a sampling node; a comparator having an input coupled to the sampling node; SAR logic having an input coupled to an output of the comparator and at least one output coupled to an input of the first DAC; a quantizer configured to generate a first digital signal representing a voltage at the sampling node; a digital filter configured to apply a filter to the first digital signal; and a second DAC configured to generate an analog signal representing the filtered first digital signal and provide the analog signal to the sampling node.

A signal processing device and a control method therefor comprise: a filter circuit including a first capacitor and reducing a predetermined frequency component of an analog signal; a sample-and-hold circuit including a second capacitor and sampling and holding the analog signal that has passed through the filter circuit; and an AD conversion circuit converting an output signal from the sample-and-hold circuit into a digital signal, and a predetermined voltage is applied to the second capacitor, thereby charging the second capacitor, and the sample-and-hold circuit is then caused to sample the analog signal that has passed through the filter circuit. This suppresses the time required to charge the first capacitor and reduces errors in digital signals.

A signal processing device and a control method therefor comprise: a filter circuit including a first capacitor and reducing a predetermined frequency component of an analog signal; a sample-and-hold circuit including a second capacitor and sampling and holding the analog signal that has passed through the filter circuit; and an AD conversion circuit converting an output signal from the sample-and-hold circuit into a digital signal, and a predetermined voltage is applied to the second capacitor, thereby charging the second capacitor, and the sample-and-hold circuit is then caused to sample the analog signal that has passed through the filter circuit. This suppresses the time required to charge the first capacitor and reduces errors in digital signals.

An analog to digital converter (ADC) that may include an input configured to receive a first signal and a second signal; a signal generator that is configured to generate multiple signals, the multiple signals may include a phase-shifted clock signals that are phase shifted from each other, first pulse width modulation (PWM) related signals indicative of a value of the first signal, second PWM related signals indicative of a value of the second signals, a first sampled stream, a second stream that have substantially opposite phases, and phase related signals related to the first sampled stream and the second sampled stream; wherein the first sampled stream and the second sampled stream are generated based on at least one of the phase shifted clock signals; and a processing unit that is configured to receive at least some of the multiple signals, the at least some of the multiple signals may include the first PWM related signals, the second PWM related signals, and the phase related signals; generate, based on the at least some of the multiple samples, virtual counter values and virtual phase values that are mutually aligned; determine a value of a difference between the first signal and the second signal, and output an ADC output signal indicative of the difference between the first signal and the second signal.

A system of an interconnected inverter includes an inverter that converts DC power from a DC power supply into AC power and provides AC power to an AC power line, an RDC that converts a voltage value obtained by a voltage sensor into electrical angle information that shows a phase angle of an output voltage, the voltage sensor obtaining a voltage value of an output voltage from the inverter to a power grid, and an ECU that controls the inverter to provide an alternating current in synchronization with an alternating current that flows through the AC power line by using timing at which an angle shown in the electrical angle information given from the RDC attains to a prescribed angle. Extra cost for diversion can be reduced.