An input sensing unit includes a touch sensing unit, which includes a plurality of driving electrodes, a plurality of sensing electrodes, and a driving signal generating unit which provides driving signals to the driving electrodes. The sensing electrodes are insulated from and intersect the driving electrodes. The driving signal generating, unit includes touch drivers connected to driving electrodes and a digital-to-analog converter configured to provide a first signal or a second signal, and each of the touch drivers is connected to a preset number of driving electrodes among the driving electrodes.

A LIDAR device includes an input node, an output node, and a sample-and-convert circuit. The input node receives a photodetector signal, and the output node generates an output signal indicating a light intensity value of the photodetector signal. The sample-and-convert circuit includes a number of detection channels coupled in parallel between the input node and the output node. In some aspects, each of the detection channels may be configured to sample a value of the photodetector signal during the sample mode and to hold the sampled value during the convert mode using a single capacitor.

A quantum circuit generator for a quantum computer includes a controller; and a plurality of analog conversion units (ACUs) operatively connected to the controller, each ACU being operatively connected to a corresponding qubit of a plurality of qubits, wherein each ACU is configured to convert a digital input from the controller into an analog input at a microwave frequency to control a quantum state of the corresponding qubit. The controller is configured to generate a quantum circuit using at least two qubits of the plurality of qubits, the at least two qubits being selected by the controller based on corresponding classical bits being mapped by the controller and based on latency of the generated quantum circuit so that the generated quantum circuit has a latency less than a threshold latency.

A communication system includes a digital data processor that produces a digital data sample and one or more control bits. A serialized transmit interface assembles the digital data sample and the control bit(s) into first and second data packets of a data frame, and sends the data frame over a signal line. A serialized receive interface receives the data frame and produces a reconstructed digital data sample and the control bit(s) from the first and second data packets. A control circuit coupled to the serialized receive interface produces a control signal from the control bit(s). The communication system may include a converter circuit, which produces an RF input signal by performing a digital-to-analog conversion of the reconstructed digital data sample, and by upconverting the resulting analog data sample signal to RF. A power amplifier amplifies the RF input signal and modifies operation of a sub-circuit based on the control signal.

A phased array may include a clock stage configured to generate shifted clock signals. Each shifted clock signal may include a different phase. The phased array may also include a beamforming stage configured to generate a beamformed signal that includes a beam formed in a direction based on summed signals. In addition, the phased array may include slices. Each slice may include a filter stage and a feedback stage. The filter stage may be configured to generate a corresponding summed signal by filtering a portion of blocker and noise interference in a corresponding receive signal based on blocking signals and the shifted clock signals. The feedback stage may be configured to generate the blocking signals based on the shifted clock signals and the corresponding summed signal. The blocking signals may be representative of the blocker and noise interference in the corresponding receive signal.

Device for generating analogue signals comprises a digital-to-analogue converter comprising at least one digital input and one analogue output, a circuit for generating a first clock signal of frequency fs, and a digital register configured so as to receive at the input and to store N bits representative of an analogue output signal of the converter, N being an integer greater than or equal to 1, and for receiving the first clock signal, the register comprising, for each bit, two complementary digital outputs.

In accordance with some embodiments of the present disclosure, an apparatus including a crossbar circuit is provided. The crossbar circuit may include a plurality of cross-point devices with programmable conductance, a transimpedance amplifier (TIA), and an analog-to-digital converter (ADC). The TIA is configured to produce an output voltage based on an input current corresponding to a summation of current from a first plurality of the cross-point devices. The ADC is configured to generate a digital output corresponding to a digital representation of the output voltage of the TIA. To generate the digital output, the ADC is to generate, using a comparator, a first plurality of bits (e.g., MSBs) of the digital output by performing a coarse conversion process and a second plurality of bits (e.g., LSBs) of the digital output by performing a fine conversion process on a sample-and-hold voltage produced in the coarse conversion process.

An analog filter, comprising, a first-time encoding machine (TEM); and a first delay element.

A digital-to-analog converter system has digital-to-analog converters, a common output, and a digital controller for transmitting first codes to one of the converters at a radio-frequency digital rate, and for transmitting second codes to another one of the converters at the same rate. The digital controller includes a timing system for operating each converter at the digital rate in a return-to-zero configuration, such that a signal from the first converter is transmitted to the common output while the second converter is reset, and vice versa. The digital-to-analog converter system can generate a radio-frequency analog signal having signals in first and second Nyquist zones simultaneously.

Systems, devices, computer-implemented methods, and/or computer program products that facilitate low power, wideband multitone generation. In one example, a multitone generator device can comprise a controller operatively coupled to first and second digital-to-analog converters (DACs). The controller can apply different delays of a sampling signal to the first and second DACs to facilitate sideband suppression of signals output by the first and second DACs. One aspect of such a multitone generator device is that the multitone generator device can facilitate low power, wideband multitone generation.