Embodiments of the present invention provide methods, systems, and computer program products for using a storlet erasure code object storage architecture for image processing. In one embodiment, an object is received, the object being represented as erasure coded bits. A storage location associated with the erasure coded bits is identified. A virtual machine (VM) is invoked, where the VM is configured to compute a modification to the erasure coded bits and replace the original erasure coded bits with the modified erasure coded bits.

Technologies for applying a redundancy encoding scheme to segmented portions of a data block include an endpoint computing device communicatively coupled to a destination computing device. The endpoint computing device is configured to divide a block of data into a plurality of data segments as a function of a transmit window size and a redundancy encoding scheme, and generate redundant data usable to reconstruct each of the plurality of data segments. The endpoint computing device is additionally configured to format a series of network packets that each includes a data segment of the plurality of data segments and generated redundant data for at least one other data segment of the plurality of data segments. Further, the endpoint computing device is configured to transport each of the series of network packets to a destination computing device. Other embodiments are described herein.

A storage system includes a first information processor, a second information processor, and a superordinate device. The first information processor includes a first memory device that stores therein the data, a difference generator that generates difference data representing a difference between updating data received from the superordinate device and the data stored in the first memory device before updating, a second memory device stores therein the generated difference data, and a data transmitter that transmits the stored difference data to the second information processor. The second information processor includes a third memory device that stores therein the parity, a data receiver that receives the difference data transmitted from the data transmitter, and a parity difference applier that generates a post-updating parity that is to be written into the third memory device by applying the received difference data to the stored parity before the updating.

A machine automation system for controlling and operating an automated machine. The system includes a controller and sensor bus including a central processing core and a multi-medium transmission intranet for implementing a dynamic burst to broadcast transmission scheme where messages are burst from nodes to the central processing core and broadcast from the central processing core to all of the nodes.

Technology for an apparatus is described. The apparatus can include a memory controller with circuitry configured to read K bits of M bits of encoded data in memory, D error detection bits, and P Parity bits protecting the M bits of encoded data for performing a read-write-modify (RWM) command operation on the K bits of the M bits encoded data, wherein K, M and D are positive integers and P is a vector of a set of parity bits. The memory controller can determine whether an error is present on the K bits of the M bits of encoded data according to the D error detection bits.

Aspects include techniques for implementing a clock path technique for using on-chip circuitry to generate a correct encode pattern to test the on-chip circuitry for encoding and correction of a chip. A computer-implemented method may include initializing a scan of the chip including data and a set of check bits protecting the data; applying a global control bit to a latch on the chip; and applying an additional clock to the latch so the check bits are updated using the on-chip circuitry.

Methods, systems, and apparatuses include receiving a codeword stored in a memory device. The codeword has bits from defective bit locations and non-defective bit locations. A syndrome of a current copy of the codeword is determined. Channel information for non-defective bit locations is determined using the current copy of the codeword and the received codeword from the memory device. Energy function values are determined for bits of the codeword using the syndrome of the current copy. Determining the energy function values includes using the channel information for bits in non-defective bit locations and omitting channel information for bits in defective bit locations. One or more bits of the codeword are flipped in response to the energy function values for the one or more bits satisfying a bit flipping criterion. A corrected codeword that results from the flipping of the bits is returned.

According to some embodiments, a method in a wireless device comprises obtaining a set of information bits for wireless transmission and dividing the set of information bits into one or more subsets of information bits. For each subset, generating extra cyclic redundancy check (CRC) bits using a CRC polynomial capable of generating N CRC bits. The extra CRC bits for each subset comprise less than N CRC bits. The method further comprises: generating a final set of N or less CRC bits for the set of information bits using the CRC polynomial; generating a set of coded bits by encoding the set of information bits for wireless transmission, together with the extra CRC bits and the final set of CRC bits, using a polar encoder; and transmitting the set of coded bits using a wireless transmitter.

A device for monitoring a digital control unit with regard to functional safety is proposed. The device comprises an interface configured to receive a control signal of the digital control unit for a circuit component. The control signal represents a digital value. Furthermore, the device comprises a timer circuit configured to output an associated timer value in each case for successive points in time. The device furthermore comprises a hash value generator, which is configurable, in response to a change in the digital value, to recalculate a hash value on the basis of the change in the digital value and the timer value at the point in time of the change in the digital value.

A method including determining a cyclic redundancy check (CRC) generator sequence defining a one to one mapping between a sequence of control information values and cyclic redundancy check (CRC) sequence values; and determining a combined sequence, the combined sequence formed by distributing the cyclic redundancy check (CRC) value sequence within the sequence of control information values, wherein the distributing the cyclic redundancy check (CRC) value sequence within the sequence of control information values is based on a selected part of the cyclic redundancy check (CRC) generator sequence.