An error correction and fault tolerance method and system for an array of disks is presented. The array comprises k+5 disks, where k disks store user data and 5 disks store computed parity. The present invention further comprises a method and a system for reconstituting the original content of each of the k+5 disks, when up to 5 disks have been lost, wherein the number of disks at unknown locations is E and the number of disks wherein the location of the disks is known is Z. All combinations of faulty disks wherein Z+2×E≤4 are reconstituted. Some combinations of faulty disks wherein Z+2×E≥5 are either reconstituted, or errors are limited to a small list.

The present disclosure is directed to systems and methods for the secure transmission of plaintext data blocks encrypted using a NIST standard encryption to provide a plurality of ciphertext data blocks, and using the ciphertext data blocks to generate a Galois multiplication-based authentication tag and parity information that is communicated in parallel with the ciphertext blocks and provides a mechanism for error detection, location and correction for a single ciphertext data block or a plurality of ciphertext data blocks included on a storage device. The systems and methods include encrypting a plurality of plaintext blocks to provide a plurality of ciphertext blocks. The systems and methods include generating a Galois Message Authentication Code (GMAC) authentication tag and parity information using the ciphertext blocks. The GMAC authentication tag may be encrypted to provide a GIMAC authentication tag that is communicated in parallel with the ciphertext blocks to one or more recipient systems or devices.

An error correction device according to the technical idea of the present disclosure includes a syndrome generation circuit configured to receive data and generate a plurality of syndromes for the data, a partial coefficient generation circuit configured to generate partial coefficient information on a part of a coefficient of an error location polynomial by using the data while the plurality of syndromes are generated, an error location determination circuit configured to determine the coefficient of the error location polynomial based on the plurality of syndromes and the partial coefficient information, and obtain a location of an error in the data by using the error location polynomial, and an error correction circuit configured to correct the error in the data according to the location of the error.

Memory controllers, devices and associated methods are disclosed. In one embodiment, a memory controller includes write circuitry to transmit write data to a memory device, the write circuitry includes a write error detection correction (EDC) encoder to generate first error information associated with the write data. Data bus inversion (DBI) circuitry conditionally inverts data bits associated with each of the write data words based on threshold criteria. Read circuitry receives read data from the memory device. The read circuitry includes a read EDC encoder to generate second error information associated with the received read data. Logic evaluates the first and second error information and conditionally reverse-inverts at least a portion of the read data based on the decoding.

Provided are a data processing method and device. The data processing method includes: performing Polar code encoding on an input bit sequence having a length of K bits to obtain an encoded bit sequence having a length of N bits, and determining a bit sequence to be transmitted from the encoded bit sequence according to a data characteristic of an information bit sequence and a predetermined rate matching scheme. K is a positive integer and N is a positive integer greater than or equal to K.

Provided are a data processing method and device. The data processing method includes: performing Polar code encoding on an input bit sequence having a length of K bits to obtain an encoded bit sequence having a length of N bits, and determining a bit sequence to be transmitted from the encoded bit sequence according to a data characteristic of an information bit sequence and a predetermined rate matching scheme. K is a positive integer and N is a positive integer greater than or equal to K.

An ECC decoder includes a syndrome calculation block, a fast path controller, a KES block, a CSEE block, an UED, and a multiplexer. The KES block includes a plurality of KES-stages to calculate and output an error location/magnitude polynomial of a syndrome outputted from the syndrome calculation block. Each of a second to last KES-stages of the plurality of KES-stages receives the error location/magnitude polynomial from the previous KES-stage to output an error location/magnitude polynomial generated by an additional calculating operation. The additionally calculated error location/magnitude polynomial is not transmitted to the next KES-stage but directly outputted when an error location and an error magnitude are identified by the additionally calculated error location/magnitude polynomial.

Reduction in deterioration of a memory cell in a non-volatile memory is achieved. A memory controller is configured to include a time measuring unit, an elapsed time determination unit, and a read unit. The time measuring unit measures time elapsed from predetermined timing on an address where data written. The elapsed time determination unit determines whether the elapsed time exceeds a fixed amount of time upon receiving an instruction to read out the data from the address. The read control unit causes reading-out of the data from the address to pause in a case where the elapsed time is determined not to exceed the fixed amount of time.

Provided are a data processing method and device. The data processing method includes: performing Polar code encoding on an input bit sequence having a length of K bits to obtain an encoded bit sequence having a length of N bits, and determining a bit sequence to be transmitted from the encoded bit sequence according to a data characteristic of an information bit sequence and a predetermined rate matching scheme. K is a positive integer and N is a positive integer greater than or equal to K.

According to some embodiments, a method in a wireless device comprises obtaining a set of information bits for wireless transmission and dividing the set of information bits into one or more subsets of information bits. For each subset, generating extra cyclic redundancy check (CRC) bits using a CRC polynomial capable of generating N CRC bits. The extra CRC bits for each subset comprise less than N CRC bits. The method further comprises: generating a final set of N or less CRC bits for the set of information bits using the CRC polynomial; generating a set of coded bits by encoding the set of information bits for wireless transmission, together with the extra CRC bits and the final set of CRC bits, using a polar encoder; and transmitting the set of coded bits using a wireless transmitter.