A syndrome calculation circuit includes a matrix product calculation circuit. The matrix product calculation circuit is configured to generate syndrome bits in a composite field by calculating a matrix product of input data bits and a first arithmetic matrix. The first arithmetic matrix is a matrix product of a basis conversion matrix for converting a data string from a Galois field to the composite field and a second arithmetic matrix, which is at least a part of a parity check matrix.

There are provided methods and systems for on-ASIC error control coding for verifying the integrity of data from a memory. For example, there is provided a method for encoding data into a beat. The method can be executed by a digital system configured to receive the data and construct the beat. The method includes assembling, by the digital system, a plurality of words consecutively. The plurality of words can include a first set of words in which each word has a length W, where W is the beat width. The plurality of words can further include a second set of words in which each word has a length that is smaller or equal to W. The method can further include constructing a parity word of length W, wherein each bit in the parity word is a parity associated with a distinct word in the first and second set of words. The method further includes adding the parity word to the plurality of words to form the beat.

There is provided a method for generating a burst error correction code. The method comprises: setting a mother code; defining a syndrome set corresponding to each burst error pattern for at least two burst error patterns to be corrected based on the mother code; shortening a column of a PCM (parity check matrix) of the mother code so that the defined syndrome sets are relatively prime; and designing an error correction code for the each burst error pattern based on an optimal generator polynomial maximizing a length of the shortened code within a range of a length of a parity bit of the mother code or a syndrome vector included in the syndrome set that is relatively prime.

A semiconductor device includes a syndrome generation circuit configured to generate a syndrome code based on data and an error correction code corresponding to the data, an error determination circuit configured to detect a 1-bit error in the data based on the syndrome code, and multi-bit error detection circuit configured to determine whether the data detected to have 1-bit error includes a multi-bit error by using an error address of the data detected to have 1-bit error and an error syndrome code of the data detected to have 1-bit error.

Method for sending first data as quantum information in qubits (Iφ>) and classical second data (S.sub.i) over a quantum channel (12; 12a; 12b), in particular in quantum information communication systems (10; 10a; 10b), which includes applying QECC encoding (111) to said qubits ((Iφ>) obtaining quantum information codewords (Iψ>), wherein said method (200; 300) includes applying (210) intentional errors (P.sub.i) with error syndromes (S.sub.i) representing said second classical data to said quantum information code-words ((Iψ>) obtaining quantum information codewords with intentional errors (P.sub.1) applied upon (P.sub.iIψ.sub.i>), and transmitting (220) from a transmitting side (11; 11a; 11b) said quantum information codewords with intentional errors applied upon (P.sub.iIψ.sub.i>) over said quantum channel (12; 12a) which outputs received codewords (P.sub.iIψ.sub.i>;E.sub.iP.sub.iIψ.sub.i>) at a receiving side (13; 13b), computing (230; 330) error syndromes (S.sub.i,R.sub.i) from said received codewords (P.sub.iIψ.sub.i>;E.sub.iP.sub.iIψ.sub.i>), performing a QECC error correction operation (250; 350) on said received codewords (P.sub.iIψ.sub.i>;E.sub.iP.sub.iIψ.sub.i>) by applying a correction operator (P.sub.i.sup.+; P.sub.i.sup.+E.sub.i.sup.+) obtained at least by said computed syndromes (S.sub.i; R.sub.i) to obtain corrected codewords (Iψ.sub.i>), outputting (260; 360) said corrected codewords (Iψ.sub.i>) and said computed syndromes (S.sub.i).

A memory includes a first check matrix calculation circuit suitable for generating a first parity by calculating a group indicator portion of a check matrix and a write data; a memory core suitable for storing the write data and the first parity; a first syndrome calculation circuit suitable for generating a first syndrome by adding the first parity which is read from the memory core to a first calculation result obtained by calculating the group indicator portion and the data which is read from the memory core; and a failure determination circuit suitable for accumulating the first syndromes for a region of the memory core to generate a vector and determining a presence of a failure of the region based on the vector.

A syndrome calculation circuit includes a matrix product calculation circuit. The matrix product calculation circuit is configured to generate syndrome bits in a composite field by calculating a matrix product of input data bits and a first arithmetic matrix. The first arithmetic matrix is a matrix product of a basis conversion matrix for converting a data string from a Galois field to the composite field and a second arithmetic matrix, which is at least a part of a parity check matrix.

Methods, systems, and devices for managing error control information using a register are described. A memory device may store, at a register, an indication of whether the memory device has detected an error included in or otherwise associated with data requested from a host device. The memory device may determine to store the indication based on whether a communication protocol is enabled or disabled, and whether an error control configuration is enabled or disabled. The host device may request information from the register of the memory device, and the memory device may output the indication of whether the error was detected in response to the request.

An error correction circuit, including an error correction code (ECC) encoder configured to generate parity data corresponding to main data based on a parity generation matrix, and to output a codeword including the main data and the parity data to a plurality of memory devices; and an ECC decoder configured to: read the codeword from the plurality of memory devices, generate a syndrome corresponding to the codeword based on a parity check matrix, detect an error pattern based on the syndrome, generate a plurality of estimation syndromes corresponding to the error pattern using a plurality of partial sub-matrices included in the parity check matrix, and correct an error included in the read codeword based on a result of a comparison between the syndrome and the plurality of estimation syndromes.

This application discloses decoding methods, apparatuses, and computer-readable storage media, which may be applied to a plurality of scenarios such as a metropolitan area network, a backbone network, and data center interconnection. An example method includes: obtaining syndromes corresponding to a plurality of codewords; grouping the syndromes into groups; and sorting priorities of each group of syndromes; and selecting, based on a priority sorting result of each group of syndromes, a syndrome for decoding.