A data processing apparatus including a frequency interleaves that includes memory configured to write and read data, and an address generator configured to produce a write address and a read address, and that writes the data to the memory in accordance with the write address and reads out the data from the memory in accordance with the read address, thereby carrying out frequency interleaving. The address generator is configured to produce a first pseudo random bit stream, produce a second pseudo random bit stream, alternately produce a bit as 0 and a bit as 1 as an additional bit added as a most significant bit of the first pseudo random bit stream, and produce the write address or the read address by obtaining an exclusive-OR between the first pseudo random bit stream having the additional bit added as the most significant bit and the second pseudo random bit stream.

A data processing apparatus including a frequency interleaves that includes memory configured to write and read data, and an address generator configured to produce a write address and a read address, and that writes the data to the memory in accordance with the write address and reads out the data from the memory in accordance with the read address, thereby carrying out frequency interleaving. The address generator is configured to produce a first pseudo random bit stream, produce a second pseudo random bit stream, alternately produce a bit as 0 and a bit as 1 as an additional bit added as a most significant bit of the first pseudo random bit stream, and produce the write address or the read address by obtaining an exclusive-OR between the first pseudo random bit stream having the additional bit added as the most significant bit and the second pseudo random bit stream.

The present technique relates to a data processing apparatus, and a data processing method each of which enables a valid address to be more reliably produced in interleave. In a data processing apparatus, a frequency interleaver for carrying out frequency interleave calculates a first bit stream produced by a first pseudo random number generating portion configured to produce a random bit stream, a second bit stream produced by a second pseudo random number generating portion configured to produce a random bit stream, and an additional bit produced by a bit producing portion configured to alternately produce a bit as 0 and a bit as 1. As a result, in producing a write address or a read address including a random bit stream, the bit as 0 and the bit as 1 are alternately repeated as the most, significant bit in the random bit stream. The present technique, for example, can be applied to a frequency interleaver for carrying out frequency interleave.

The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE). Method and apparatus for interleaving is provided. The method includes the following steps: constructing a plurality of pseudorandom sequences according to a pre-defined length of an interleaving sequence to be constructed; for each of the constructed pseudorandom sequences, constructing at least one corresponding numerical digit random sequence according to a number of more than two types of numerical values in this pseudorandom sequence; and, for each of the constructed pseudorandom sequences and the at least one corresponding numerical digit random sequence thereof, constructing a corresponding interleaving sequence according to a mapping relation between this pseudorandom sequence and the numerical digit random sequence, so that a plurality of interleaving sequences are allocated and indicated as multiple access signatures.

The present technique relates to a data processing apparatus, and a data processing method each of which enables a valid address to be more reliably produced in interleave.

In a data processing apparatus, a frequency interleaver for carrying out frequency interleave calculates a first bit stream produced by a first pseudo random number generating portion configured to produce a random bit stream, a second bit stream produced by a second pseudo random number generating portion configured to produce a random bit stream, and an additional bit produced by a bit producing portion configured to alternately produce a bit as 0 and a bit as 1. As a result, in producing a write address or a read address including a random bit stream, the bit as 0 and the bit as 1 are alternately repeated as the most significant bit in the random bit stream. The present technique, for example, can be applied to a frequency interleaver for carrying out frequency interleave.

The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE). Method and apparatus for interleaving is provided. The method includes the following steps: constructing a plurality of pseudorandom sequences according to a pre-defined length of an interleaving sequence to be constructed; for each of the constructed pseudorandom sequences, constructing at least one corresponding numerical digit random sequence according to a number of more than two types of numerical values in this pseudorandom sequence; and, for each of the constructed pseudorandom sequences and the at least one corresponding numerical digit random sequence thereof, constructing a corresponding interleaving sequence according to a mapping relation between this pseudorandom sequence and the numerical digit random sequence, so that a plurality of interleaving sequences are allocated and indicated as multiple access signatures.