Patent classifications
H03M13/2757
Efficient interleaver design for polar codes
Aspects of the disclosure relate to wireless communication devices configured to encode information blocks to produce code blocks and interleave the code blocks utilizing an interleaver including a plurality of rows and a plurality of columns, where the number of columns of the interleaver varies between the rows. In some examples, the interleaver includes a right isosceles triangle-shaped matrix of rows and columns. In other examples, the interleaver includes a trapezoid-shaped matrix of rows and columns.
EFFICIENT INTERLEAVER DESIGN FOR POLAR CODES
Aspects of the disclosure relate to wireless communication devices configured to encode information blocks to produce code blocks and interleave the code blocks utilizing an interleaver including a plurality of rows and a plurality of columns, where the number of columns of the interleaver varies between the rows. In some examples, the interleaver includes a right isosceles triangle-shaped matrix of rows and columns. In other examples, the interleaver includes a trapezoid-shaped matrix of rows and columns.
Data processing device and data processing method
The present technology relates to a data processing device and a data processing method, which are capable of securing excellent communication quality in data transmission using an LDPC code. In group-wise interleave, an LDPC code in which a code length N is 16200 bits and an encoding rate r is 6/15, 8/15, or 10/15 is interleaved in units of bit groups of 360 bits. In group-wise deinterleave, a sequence of the LDPC code that has undergone the group-wise interleave is restored to an original sequence. For example, the present technology can be applied to a technique of performing data transmission using an LDPC code.
EFFICIENT INTERLEAVER DESIGN FOR POLAR CODES
Aspects of the disclosure relate to wireless communication devices configured to encode information blocks to produce code blocks and interleave the code blocks utilizing an interleaver including a plurality of rows and a plurality of columns, where the number of columns of the interleaver varies between the rows. In some examples, the interleaver includes a right isosceles triangle-shaped matrix of rows and columns. In other examples, the interleaver includes a trapezoid-shaped matrix of rows and columns.
Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 7/15 and quadrature phase shift keying, and bit interleaving method using same
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 7/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.
Transmitting apparatus, and puncturing method thereof
There is provided a transmitting apparatus. The transmitting apparatus includes an encoder configured to perform Low Density Parity Check (LDPC) encoding with respect to input data, based on a parity check matrix, a parity interleaver configured to interleave parity bits from among LDPC codewords generated by the LDPC encoding, and a puncturer configured to puncture at least a part of the interleaved parity bits, and the puncturer groups the parity bits based on an interval at which a pattern of columns is repeated in an information word sub matrix constituting the parity check matrix and perform puncturing based on the number of punctured parity bits and a position of punctured parity bit groups from among the grouped parity bit groups.
Apparatus and method for transmitting/receiving signal in communication system supporting bit-interleaved coded modulation with iterative decoding scheme
The present disclosure relates to a pre-5.sup.th-generation (5G) or 5G communication system to be provided for supporting higher data rates beyond 4.sup.th-generation (4G) communication system such as a long term evolution (LTE). A method for transmitting a signal in a signal transmitting apparatus in a communication system supporting a bit-interleaved coded modulation with iterative decoding (BICM-ID) scheme is provided. The method includes performing an outer encoding operation; performing an interleaving operation on the outer code corresponding to an interleaving scheme which is based on a preset generation matrix to generate an interleaved signal; performing an inner encoding operation; performing a modulating operation; and transmitting the modulated signal, wherein the generation matrix is generated by applying at least one of a preset column permutation rule and a preset row permutation rule to a generation matrix for a quasi-cyclic (QC) interleaver.
Data storage device encoding and interleaving codewords to improve trellis sequence detection
A data storage device is disclosed comprising a storage medium. First data is encoded into a first codeword, and second data is encoded into a second codeword, wherein a first code rate of the first codeword is less than a second code rate of the second codeword. The first codeword and the second codeword are interleaved to generate an interleaved codeword that is written to the storage medium.
Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 7/15 and quadrature phase shift keying, and bit interleaving method using same
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 7/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.
STORAGE ERROR CORRECTION USING CYCLIC-CODE BASED LDPC CODES
Techniques are described for joint encoding and decoding of information symbols. In one embodiment, a method for joint encoding includes, in part, obtaining a sequence of information symbols, generating a plurality of cyclic codewords each corresponding to a portion of the sequence of information symbols, jointly encoding the plurality of cyclic codewords to generate at least one combined codeword, and providing the combined codeword to a device. The at least one combined codeword may be generated through Galois Fourier Transform (GFT). In one embodiment, a method for joint decoding includes, in part, obtaining a sequence of encoded symbols, wherein the sequence of encoded symbols is generated through GFT, jointly decoding the sequence of encoded symbols using an iterative soft decision decoding algorithm to generate a decoded sequence, transforming the decoded sequence to generate a plurality of cyclic codewords, and decoding the plurality of cyclic codewords to generate a plurality of decoded information symbols.