Patent classifications
H03M13/2771
SYSTEMS AND METHODS OF DECODING ERROR CORRECTION CODE OF A MEMORY DEVICE WITH DYNAMIC BIT ERROR ESTIMATION
A method, of decoding error correction code of a memory device with dynamic bit error estimation, can include generating at least one metric corresponding to one or more syndromes associated with a code word, the code word comprising an error correction code of a memory device, decoding the code word by a first decoder integrated with the memory device, in response to a determination that the metric satisfies a threshold associated with the syndromes, the first decoder having a first execution property, and decoding the code word by a second decoder integrated with the memory device, in response to a determination that the metric does not satisfy the threshold associated with the syndromes, the second decoder having a second execution property distinct from the first execution property, or in response to a determination that the metric satisfies the threshold associated with the syndromes, and in response to a determination to perform further decoding.
INTERLEAVER DESIGN AND PAIRWISE CODEWORD DISTANCE DISTRIBUTION ENHANCEMENT FOR TURBO AUTOENCODER
A symmetric interleaver for a Convolutional Neural Network (CNN) and Recurrent Neural Network (RNN) encoder and a circular padding mode are disclosed. The interleaver interleaves elements of an input block to form an output block in which an output neighborhood of elements for each element of the output block is symmetric to an input neighborhood of elements for each element of the input block. A position of an element of the input block is interleaved based on an index i of the position times a parameter δ modulo K in which the parameter δ is relatively prime with K. A test loss function may be used to train the encoder that includes a Binary Cross Entropy (BCE) loss function plus a function that minimizes a number of codeword pairs based on a Euclidean distance. The RNN encoder may be implemented as part of a Turbo Autoencoder (TurboAE) encoder.
Method for generating a signal by means of a turbo-encoder, and corresponding device and computer program.
A method for generating a signal, including turbo-coding a set of information symbols delivering, on the one hand, the information symbols and, on the other hand, redundancy symbols. The turbo-coding implementing, to obtain the redundancy symbols: an encoding of the set of information symbols by a first encoder, an interleaving of the set of information symbols, and an encoding of the set of information symbols interleaved by a second encoder. The turbo-coding also implements a bijective transformation of the information symbols, implemented before and/or after the interleaving, the transformation modifying a value of at least two of the information symbols prior to the coding of the information symbols by the first and/or the second coder.
FULLY PARALLEL TURBO DECODING
A detection circuit performs a turbo detection process to recover a frame of data symbols from a received signal, the data symbols of the frame having been effected, during transmission, by a Markov process with the effect that the data symbols of the frame in the received signal are dependent one or more preceding data symbols which can be represented as a trellis having a plurality of trellis stages. The detection circuit comprises a plurality of processing elements, each of the processing elements is associated with one of the trellis stages representing the dependency of the data symbols of the frame according to the Markov process and each of the processing elements is configured to receive one or more soft decision values corresponding to one or more data symbols associated with the trellis stage, and each of one or more of the processing elements is configured, in one clock cycle to receive fixed point data representing a priori forward state metrics a priori backward state metrics, and fixed point data representing a priori soft decision values for the one or more data symbols being detected for the trellis stage. For each of a plurality of clock cycles of the turbo detection process, the detection circuit is configured to process, for each of the processing elements representing the trellis stages, the a priori information for the one or more data symbols being detected for the trellis stage associated with the processing element, and to provide the extrinsic soft decision values corresponding to the one or more data symbols for a next clock cycle of the turbo detection process.
PARALLELIZABLE REDUCED STATE SEQUENCE ESTIMATION VIA BCJR ALGORITHM
An apparatus and method for optimizing the performance of satellite communication system receivers by using the Soft-Input Soft-Output (SISO) BCJR (Bahl, Cocke, Jelinek and Raviv) algorithm to detect a transmitted information sequence is disclosed. A Sliding Window technique is used with a plurality of reduced state sequence estimation (RSSE) equalizers to execute the BCJR algorithm in parallel. A serial data stream is converted into a plurality of data blocks using a serial-to-parallel converter. After processing in parallel by the equalizers, the output blocks are converted back to a serial data stream by a parallel-to-serial converter. A path history is determined using maximum likelihood (ML) path history calculation.
DOUBLE FACTOR CORRECTION TURBO DECODING METHOD BASED ON SIMULATED ANNEALING ALGORITHM
A double factor correction Turbo decoding method based on a simulated annealing algorithm is provided, including: S1: setting an initial bit error rate P.sub.e0 and an initial solution of correction factors; S2: randomly selecting a new solution of the correction factors from a proximinal subset of a current solution, and calculating a new bit error rate P.sub.enew; S3: determining whether the new bit error rate is smaller than a bit error rate of a previous decoding, and if so, receiving the new solution of the correction factors, otherwise calculating a reception probability based on a difference between the new bit error rate and the bit error rate of the previous decoding; S4: decreasing the initial bit error rate P.sub.e0 to determine whether a termination condition is satisfied, performing S5 if the termination condition is satisfied, otherwise performing S2; and S5: outputting a current solution of the correction factors as an optimal solution.
Double factor correction turbo decoding method based on simulated annealing algorithm
A double factor correction Turbo decoding method based on a simulated annealing algorithm is provided, including: S1: setting an initial bit error rate P.sub.e0 and an initial solution of correction factors; S2: randomly selecting a new solution of the correction factors from a proximal subset of a current solution, and calculating a new bit error rate P.sub.enew; S3: determining whether the new bit error rate is smaller than a bit error rate of a previous decoding, and if so, receiving the new solution of the correction factors, otherwise calculating a reception probability based on a difference between the new bit error rate and the bit error rate of the previous decoding; S4: decreasing the initial bit error rate P.sub.e0 to determine whether a termination condition is satisfied, performing S5 if the termination condition is satisfied, otherwise performing S2; and S5: outputting a current solution of the correction factors as an optimal solution.
Method for generating a signal by means of a turbo-encoder, and corresponding device and computer program
A method for generating a signal, including turbo-coding a set of information symbols delivering, on the one hand, the information symbols and, on the other hand, redundancy symbols. The turbo-coding implementing, to obtain the redundancy symbols: an encoding of the set of information symbols by a first encoder, an interleaving of the set of information symbols, and an encoding of the set of information symbols interleaved by a second encoder. The turbo-coding also implements a bijective transformation of the information symbols, implemented before and/or after the interleaving, the transformation modifying a value of at least two of the information symbols prior to the coding of the information symbols by the first and/or the second coder.
Turbo product polar coding with hard decision cleaning
An encoder for encoding source information into an encoded codeword used in a communication channel includes a data input to receive source data, a processor, and a memory to store an encoder program. The encoder program makes the processor to encode the source data into a turbo product coding (TPC) structure, and the TPC structure comprises a data block corresponding to the source data, a first parity block including a first column part, a first corner part and a first bottom part, the first parity block being arranged so as to cover a right end column of the data block, a right bottom corner of the data block and a bottom row of the data block by the first column part, the first corner part and the first bottom part, and a second parity block having a row parity block, a joint parity block and a column parity block.
TURBO ENCODING METHOD, TURBO ENCODER AND UAV
A turbo encoding method includes obtaining a code block for turbo encoding, storing a data block of the code block in a plurality of parallel caches, and obtaining parallel data from the plurality of parallel caches for turbo encoding.