H03M13/336

Low latency data transfer technique for mesochronous divided clocks

Electrical circuits and associated methods relate to performing a phase alignment by providing N copies of clock alignment circuits, enabling and selecting different clock alignment circuits to achieve an initial phase alignment. In an illustrative example, a phase alignment circuit may include a first clock alignment circuit configured to find a first phase alignment point and a second clock alignment circuit configured to find a second phase alignment point. A control circuit may be configured to select a primary clock alignment circuit from the first clock alignment circuit and the second clock alignment circuit and generate a digital command signal to control a phase interpolator. In various embodiments, by setting the control circuit, the same phase alignment circuit may be used to perform phase alignments between clock domains with different frequencies.

Symbol timing recovery based on speculative tentative symbol decisions

A method for timing recovery for a high-speed data transmission system may be provided. The method comprises receiving an analog input signal at an ADC and passing processed digital signal samples to a Viterbi detector. The method also comprises receiving at least one processed signal sample and at least two sets of at least one candidate symbol each from the Viterbi detector and/or the processed signal samples by timing error detectors and forwarding output digital signals of the timing error detectors via loop filters to related multiplexers. Furthermore, the method comprises selecting one digital signal from each of the multiplexers using a select signal generated by the Viterbi detector, and deriving a control signal controlling a sampling clock of the analog-to-digital converter by at least one of the selected digital signals from the multiplexers.

Signal processing method, apparatus and signal receiver
09942071 · 2018-04-10 · ·

The present application discloses a method for processing a signal. An apparatus detects, according to a check relationship set during a forward error correction coding, that a phase jump occurs in a data segment of a signal, and a quantity of degrees of the phase jump, performs, according to the quantity of degrees of the phase jump, a phase correction on the data segment; after the phase correction, performs a confidence correction on the data segment; and after the confidence correction, performs a forward error correction decision decoding on the data segment on which the confidence correction has been performed and output the data segment.

Forward error correction with turbo/non-turbo switching

A forward error correction and differentially encoded signal obtained via a communication channel is supplied to a soft-input soft-output (SISO) differential decoder that is bi-directionally coupled to a SISO forward error correction decoder. Over a first portion of a plurality of decoding iterations of the differentially encoded signal, the SISO differential decoder and the SISO forward error correction decoder are operated in a turbo decoding mode in which decoded messages generated by the SISO differential decoder are supplied to the SISO forward error correction decoder and forward error correction messages are supplied to the differential decoder. Over a second portion of the plurality of decoding iterations of the differentially encoded signal, the SISO forward error correction decoder is operated in a non-turbo decoding mode without any messages passing to and from the SISO differential decoder. Decoder output is obtained from the SISO forward error correction decoder.

Forward error correction with turbo/non-turbo switching

A forward error correction and differentially encoded signal obtained via a communication channel is supplied to a soft-input soft-output (SISO) differential decoder that is bi-directionally coupled to a SISO forward error correction decoder. Over a first portion of a plurality of decoding iterations of the differentially encoded signal, the SISO differential decoder and the SISO forward error correction decoder are operated in a turbo decoding mode in which decoded messages generated by the SISO differential decoder are supplied to the SISO forward error correction decoder and forward error correction messages are supplied to the differential decoder. Over a second portion of the plurality of decoding iterations of the differentially encoded signal, the SISO forward error correction decoder is operated in a non-turbo decoding mode without any messages passing to and from the SISO differential decoder. Decoder output is obtained from the SISO forward error correction decoder.

FORWARD ERROR CORRECTION WITH TURBO/NON-TURBO SWITCHING
20170117924 · 2017-04-27 ·

A forward error correction and differentially encoded signal obtained via a communication channel is supplied to a soft-input soft-output (SISO) differential decoder that is bi-directionally coupled to a SISO forward error correction decoder. Over a first portion of a plurality of decoding iterations of the differentially encoded signal, the SISO differential decoder and the SISO forward error correction decoder are operated in a turbo decoding mode in which decoded messages generated by the SISO differential decoder are supplied to the SISO forward error correction decoder and forward error correction messages are supplied to the differential decoder. Over a second portion of the plurality of decoding iterations of the differentially encoded signal, the SISO forward error correction decoder is operated in a non-turbo decoding mode without any messages passing to and from the SISO differential decoder. Decoder output is obtained from the SISO forward error correction decoder.

Kalman filter based phase-locked loop with re-encoding based phase detector

A wireless communications device includes a receiver having a phase detector configured to extract frequency offset and provide a corresponding error signal generated based on a baseband version of a received radio frequency signal and an expected transmitted data signal. The receiver has a phase-locked loop configured to generate an error correction signal based on a phase of the error signal and a predicted instantaneous phase of the error signal. The receiver has a correction circuit configured to provide a corrected baseband version of the received radio frequency signal based on the baseband version of the received radio frequency signal and the error correction signal. The receiver may have a re-encoding-based processing circuit configured to provide the expected transmitted data signal based on a preliminarily decoded symbol.