Patent classifications
H03M13/3738
PROTOCOL DATA UNIT (PDU) ERROR PROBABILITY FEEDBACK
Systems, methods, apparatuses, and computer program products for error probability feedback are provided. One method may include transmitting, to at least one user equipment, a configuration for protocol data unit error probability calculation and reporting. The method may also include receiving, from the at least one user equipment, feedback related to the protocol data unit error probability.
Performing a decoding operation to simulate switching a bit of an identified set of bits of a data block
A set of bits of a segment of a memory device that is associated with an unsuccessful first decoding operation can be identified. A discrepancy value for at least one bit of the set of bits can be calculated. It can be determined whether the discrepancy value calculated for the at least one bit of the set of bits corresponds to a correction capability of the failed decoding operation. In response to determining that the discrepancy value calculated for the at least one bit corresponds to the correction capability of the failed decoding operation, the at least one bit of the set of bits can be corrected by switching a value of the at least one bit.
SYSTEMS AND METHODS OF DECODING ERROR CORRECTION CODE OF A MEMORY DEVICE WITH DYNAMIC BIT ERROR ESTIMATION
A method, of decoding error correction code of a memory device with dynamic bit error estimation, can include generating at least one metric corresponding to one or more syndromes associated with a code word, the code word comprising an error correction code of a memory device, decoding the code word by a first decoder integrated with the memory device, in response to a determination that the metric satisfies a threshold associated with the syndromes, the first decoder having a first execution property, and decoding the code word by a second decoder integrated with the memory device, in response to a determination that the metric does not satisfy the threshold associated with the syndromes, the second decoder having a second execution property distinct from the first execution property, or in response to a determination that the metric satisfies the threshold associated with the syndromes, and in response to a determination to perform further decoding.
Decoding System, Decoding Controller, and Decoding Control Method
A decoding system, a decoding controller, and a decoding control method are provided. In the decoding system, a decoding controller is disposed between two adjacent decoders. The decoding controller determines whether to perform turn-off based on a non-turn-off indication received by a previous-stage decoder, a turn-off indication output by the previous-stage decoder, and historical turn-off probability statistics. This is equivalent to adding a buffer zone between the two adjacent decoders.
Systems and methods for detecting or preventing false detection of three error bits by SEC
Various implementations described herein relate to correcting errors in Dynamic Random Access Memory (DRAM). A memory controller uses an Error Correcting Code (ECC) to store an encoded data word within a DRAM die. The DRAM die is communicatively coupled the memory controller by a memory data bus. The DRAM die includes on-die error correction for data bits stored in the DRAM. Upon reading the encoded data word, the memory controller corrects and detects one or more errors. The one or more errors are introduced by at least one of the on-die error correction of the DRAM die or the memory data bus.
Dynamic multi-stage decoding
Methods and systems for decoding raw data may include determining a sequence of a plurality of read-level voltages based on previous decoding data and executing a multi-stage decoding operation to decode raw data read from the plurality of memory cells using the determined sequence of the plurality of read-level voltages. Decoded data is returned from the multi-stage decoding operation upon completion of the multi-stage decoding operation and the previous decoding data is updated based on results of the multi-stage decoding operation.
METHOD AND SYSTEM FOR ERROR CHECKING IN WIRELESS COMMUNICATIONS
A method and system for error checking in a wireless communication are provided. The method includes: receiving a payload; determining a final decoding result of the payload, the final decoding result indicating a start state and an end state; determining whether the end state is identical to the start state based on a state circularity check; and determining to discard the final decoding result based on whether the end state is identical to the start state.
Early decoding termination for a memory sub-system
A method includes receiving a request for host data, receiving a codeword that is associated with the host data, performing a decoding operation for a first portion of the codeword to generate a segment of decoded data, determining whether the segment of the decoded data satisfies the request for the host data, and in response to determining that the segment of the decoded data satisfies the request for the host data, terminating the decoding operation for remaining portions of the codeword.
DATA INTERPRETATION WITH MODULATION ERROR RATIO ANALYSIS
Methods and systems for analyzing data are disclosed. An example method can comprise receiving a first data signal, decoding the first data signal, determining a second data signal based on the decoded first data signal, and determining a modulation error ratio based on a difference between the first data signal and the second data signal.
Data checking method and device
Provided are a data checking method and device. The method includes: receiving a transmission signal containing a first data block and transmitted by a transmission node, wherein the length of the first data block is N bits, the first data block is generated by performing an FEC encoding on a second data block which has a length of K bits, and the second data block is generated by performing a CRC encoding on a third data block which has a length of L bits, where N, K and L are all positive integers, and N≧K>L; obtaining a first estimation data block of the first data block according to the transmission signal, and obtaining a second estimation data block of the second data block according to the transmission signal; and checking the third data block according to a relationship between the first estimation data block and an FEC code space and/or a CRC check result of the second estimation data block. By means of the technical solution provided in the present disclosure, the problems that a transmission rate decreases due to the fact that a CRC check code is too long and a false detection rate cannot be ensured due to the fact that the CRC check code is too short are solved.