One example of layer-by-layer error correction can include iteratively error correcting the codeword on a layer-by-layer basis with the first error correction circuit in a first mode and determining on the layer-by-layer basis whether a number of parity errors in a particular layer is less than a threshold number of parity errors. The codeword can be transferred to a second error correction circuit when the number of parity errors is less than the threshold number of parity errors. The codeword can be iteratively error corrected with the first error correction circuit in a second mode when the number of parity errors is at least the threshold number of parity errors. The threshold number of parity errors can be at least partially based on an adjustable code rate of the first error correction circuit or the second error correction circuit.

Methods, systems, and apparatuses include receiving a codeword stored in a memory device. The codeword is error corrected for a first number of iterations. The error correction includes traversing the codeword according to a first order. The codeword is error corrected for a second number of the iterations. The error correction of the codeword during a second iteration from the second number of iterations includes traversing the codeword according to a second order that is different from the first order.

A decoding system, a decoding controller, and a decoding control method are provided. In the decoding system, a decoding controller is disposed between two adjacent decoders. The decoding controller determines whether to perform turn-off based on a non-turn-off indication received by a previous-stage decoder, a turn-off indication output by the previous-stage decoder, and historical turn-off probability statistics. This is equivalent to adding a buffer zone between the two adjacent decoders.

A method includes calculating a number of iterative detection and decoding (IDD) iterations and a number of decoding iterations for each of a plurality of channel coding units in a target codeword; calculating a demodulation time and a decoding time for the target codeword based on the number of IDD iterations and the number of decoding iterations for the target codeword; adding the target codeword to a codeword set, based on a demodulation time and a decoding time for codewords in the codeword set and the target codeword; and performing an IDD operation based on a number of IDD iterations and a number of decoding iterations.

A forward error correction (FEC) decoder is configured to find an alignment of a code block in a data stream by attempting to fully or partially decode one or more data windows of a predetermined size in the data stream. The predetermined size is a size of each codeword. The FEC decoder selects a first data window of the predetermined size, attempts to decode the first data window based on a particular error control coding method, and determines whether a valid codeword can be identified by attempting to decode the first data window. In response to determining that a valid codeword can be identified, the FEC decoder determines that an alignment of the codeword with the first data window is found. Otherwise, the FEC decoder selects a second data window of the predetermined size and attempts to decode the second data window.

A polar code decoding apparatus according to an embodiment includes a divider configured to generate a decoding tree in which a plurality of nodes including one or more critical sets for a polar-encoded codeword are formed in a hierarchical structure, and divide the decoding tree into one or more partitions, each partition equally including lowest nodes of the decoding tree, a determiner configured to determine a memory size for storing a primary decoding result based on a specific partition, the specific partition being selected from among the one or more partitions based on the number of critical sets included in each partition, and a decoder configured to decode the codeword primarily by using a successive cancellation (SC) decoding technique.

A memory controller performs an error recovery operation. The controller performs a read operation on a select block using a select read level; decodes data associated with the read operation to generate a syndrome value; determines whether to stop, before a maximum number of iterations, the read operation and the decoding at the select read level, using the syndrome value; when it is determined to stop the read operation and the decoding at the select read level, selects a next read level in a sequence of read levels; and uses the next read level for a subsequent read operation.

A turbo equalization device includes equalization circuitry, which in operation, performs an equalization process M times on an input signal, M being an integer equal to or more than 1; counter circuitry, which in operation, counts an iteration number m that indicates a number of the performed equalization process, m being an integer equal to or more than 0 and equal to less than M; control circuitry, which in operation, determines an iteration number N of a decoding process for the m times equalization processed input signal according to the iteration number m of the equalization process, the decoding process using an error correcting code that uses a belief propagation algorithm, N being an integer equal to or more than 1; and decoding circuitry, which in operation, performs a decoding process N or less times on the m times equalization processed input signal.

A method, apparatus and system for feeding back early stop decoding are provided. The method includes: a terminal side adjusting encoded TFCI bits, and sending the adjusted TFCI bits to a NodeB side via a TFCI domain of an uplink DPCCH (S302); after sending the adjusted TFCI bits to the NodeB side, the terminal side performing a decoding operation on a downlink DPCH, and feeding back, via an idle TFCI domain of the uplink DPCCH, a decoding result to the NodeB side (304). By applying the technical solution, at least one of the problems in the related art that a NodeB cannot obtain a TFCI in time and a terminal side cannot feed back a downlink decoding result in time during early stop decoding can be solved.

A decoder performs: computing (S501) a value (i,j) of a performance-improvement metric for each kernel K.sub.i,j; and sorting (S502) the kernels in a list in decreasing order of the values (i,j). The decoder then performs a beliefs propagation iterative process as follows: updating (S503) output beliefs for the W top kernels of the list , and propagating said output beliefs as input beliefs of the neighbour kernels of said W top kernels; updating (S504) output beliefs for each neighbour kernel of said W top kernels following update of their input beliefs, and re-computing (S505) the performance-improvement metric value (i,j) for each said neighbour kernel; setting (S505) the performance-improvement metric for said W top kernels to a null value; and re-ordering (S506) the kernels in the list . Then, the decoder repeats the beliefs propagation iterative process until a stop condition is met.