Patent classifications
H03M13/3769
Calculating soft metrics depending on threshold voltages of memory cells in multiple neighbor word lines
A memory controller includes an interface and a processor. The interface communicates with memory cells organized in multiple Word Lines (WLs). The processor is configured to read a Code Word (CW) of an Error Correction Code (ECC) from a group of multiple memory cells belonging to a target WL, to calculate for a given memory cell (i) a first soft metric, depending on a first threshold voltage of a first neighbor memory cell in a first WL neighboring the target WL, and (ii) a second soft metric, depending on a second threshold voltage of a second neighbor memory cell in a second WL neighboring the target WL, to calculate a combined soft metric based on both the first and second soft metrics and assign the combined soft metric to the given memory cell, and to decode the CW based on the combined soft metric, to produce a decoded CW.
Transmitter and method for generating additional parity thereof
A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate an LDPC codeword including the input bits and parity bits to be transmitted in a current frame; a parity permutator configured to perform by group-wise interleaving a plurality of bit groups configuring the parity bits based on a group-wise interleaving pattern comprising a first pattern and a second pattern; a puncturer configured to puncture some of the parity-permutated parity bits; and an additional parity generator configured to select at least some of the punctured parity bits to generate additional parity bits to be transmitted in a previous frame of the current frame, based on the first pattern and the second pattern.
Signal correction using soft information in a data channel
Example systems, read channel circuits, data storage devices, and methods to provide signal correction based on soft information in a read channel are described. The read channel circuit includes a soft output detector, such as a soft output Viterbi algorithm (SOVA) detector, and a signal correction circuit. The soft output detector passes detected data bits and corresponding soft information to the signal correction circuit. The signal correction circuit uses the soft information to determine a signal correction value, which is combined with input signal to return a corrected signal to the soft output detector for a next iteration. In some configurations, the signal correction value may compensate for DC offset, AC coupling poles, and/or signal asymmetries to reduce baseline wander in the read channel.
Retransmission Softbit Decoding
Disclosed are methods and systems for using softbit decoding techniques in retransmission-based networks for error concealment of packets corrupted by bit-errors. The softbit decoding techniques derive softbit information from multiple corrupted hardbits of the retransmitted packet to aid a softbit decoder in decoding the packet. The approach realizes improved error concealment capability while maintaining a simple system architecture. A retransmission softbit module is inserted between a channel decoder used for channel-decoding and demodulating a compressed packet and the softbit decoder. The retransmission softbit module may derive an accumulated softbit packet from multiple corrupted copies of the packet received from the channel decoder, make bit decisions based on the accumulated softbit packet, and derive reliability information for the bit decisions. The bit decisions may be a majority decision packet (MDP) created using a majority voting scheme. The reliability information and the MDP may be provided to the softbit decoder for decoding.
DEVICE AND METHOD FOR ACQUIRING SYSTEM INFORMATION BY DECODING SIGNALS IN WIRELESS COMMUNICATION SYSTEM
The present disclosure relates to a pre-5.sup.th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4.sup.th-Generation (4G) communication system such as Long Term Evolution (LTE). According to various embodiments, a device of a terminal, in a wireless communication system, can comprise at least one processor and at least one transceiver operatively coupled to the at least one processor. The at least one transceiver configured to receive, from a base station, a first signal transmitted using a first beam of the base station and including system information and receive, from the base station, a second signal transmitted using a second beam of the base station and including the system information, and the at least one processor is configured to decode the second signal in combination with the first signal, thereby enabling the system information to be acquired.
Apparatus and method for encoding and decoding channel in communication or broadcasting system
The present invention related to a 5G or pre-5G communication system to be provided to support a higher data transmission rate since 4G communication systems like LTE. The present invention relates to a method and an apparatus for encoding a channel in a communication or broadcasting system supporting parity-check matrices having various sizes are provided. The method for encoding a channel includes determining a block size of the parity-check matrix; reading a sequence for generating the parity-check matrix, and transforming the sequence by applying a previously defined operation to the sequence based on the determined block size.
DECODING METHOD AND APPARATUS, NETWORK DEVICE, AND STORAGE METHOD
A decoding method and apparatus, a network device, and a storage medium are provided. The method includes: receiving data before de-interleaving and soft bit encoding locations; dividing the data before de-interleaving to obtain first data banks; acquiring punctured data, and obtaining second data banks according to the punctured data, wherein the data before de-interleaving and the punctured data are determined in encoded data according to the soft bit encoding locations; and performing decoding according to the soft bit encoding locations, the first data banks and the second data banks, so as to obtain decoded data.
ERROR RECOVERY USING ADAPTIVE LLR LOOKUP TABLE
Systems and methods are provided for performing error recovery using LLRs generated from multi-read operations. A method may comprise selecting a set of decoding factors for a multi-read operation to read a non-volatile storage device multiple times. The set of decoding factors may include an aggregation mode for aggregating read results of multiple reads. The method may further comprise issuing a command to the non-volatile storage device to read user data according to the set of decoding factors, generating a plurality of Log-Likelihood Ratio (LLR) values using a mapping engine from a pre-selected set of LLR value magnitudes based on the set of decoding factors, obtaining an aggregated read result in accordance with the aggregation mode and obtaining an LLR value from the plurality of LLR values using the aggregated read result as an index.
Method for linear encoding of signals for the redundant transmission of data via multiple optical channels
A method for the redundant transmission of data by means of light-based communication may include a data stream to be transmitted that is converted into symbols. This data stream is converted from bipolar symbols into multiple partial data streams having e.g. unipolar-positive symbols. The partial data streams are converted into multiple semi-redundant signals that are then transmitted to the receiver via multiple light-based channels. In the receiver, the received signals are converted back again analogously to when they were sent, in order to obtain the original data stream again.
Transmitter and repetition method thereof
A transmitter is provided. The transmitter includes: a low density parity check (LDPC) encoder configured to encode input bits to generate an LDPC codeword including the input bits and parity bits; a repeater configured to select at least a part of bits constituting the LDPC codeword and add the selected bits after the input bits; and a puncturer configured to puncture at least a part of the parity bits.