Methods and apparatuses for generating optimized LDPC codes are proposed. One of the methods is a method for generating an optimized LDPC code for an asymmetric transmis¬ sion channel. The method includes receiving an initial LDPC code for the asymmetric transmission channel. Further, the method includes performing a density evolution threshold optimization for the initial LDPC code in order to obtain the optimized LDPC code for the asymmetric transmission channel. A uniformly mixed symmetric channel density for the asymmetric transmission channel is used in the density evolution threshold optimization.

Methods and apparatuses for generating optimized LDPC codes are proposed. One of the methods is a method for generating an optimized LDPC code for an asymmetric transmission channel. The method includes receiving an initial LDPC code for the asymmetric transmission channel. Further, the method includes performing a density evolution threshold optimization for the initial LDPC code in order to obtain the optimized LDPC code for the asymmetric transmission channel. A uniformly mixed symmetric channel density for the asymmetric transmission channel is used in the density evolution threshold optimization.

The present disclosure provides a circuit. The circuit includes a detection circuit, a correction circuit and an adjustment circuit. The detection circuit is configured to detect an initial logic state of an input signal, and to generate, in response to the initial logic state, a first signal with a first logic state. The correction circuit is configured to compare the first signal having the first logic state with a second signal having a second logic state, and to generate an enable signal according to the comparison. The adjustment circuit is configured to be enabled by the enable signal when the first logic state of the first signal is different from the second logic state of the second signal, to generate an adjustment signal to the detection circuit, in which the detection circuit is further configured to be adjusted according to the adjustment signal, to generate an adjusted first signal.

The present disclosure provides a circuit. The circuit includes a detection circuit, a correction circuit and an adjustment circuit. The detection circuit is configured to detect an initial logic state of an input signal, and to generate, in response to the initial logic state, a first signal with a first logic state. The correction circuit is configured to compare the first signal having the first logic state with a second signal having a second logic state, and to generate an enable signal according to the comparison. The adjustment circuit is configured to be enabled by the enable signal when the first logic state of the first signal is different from the second logic state of the second signal, to generate an adjustment signal to the detection circuit, in which the detection circuit is further configured to be adjusted according to the adjustment signal, to generate an adjusted first signal.

The present disclosure provides a circuit. The circuit includes a detection circuit, a correction circuit and an adjustment circuit. The detection circuit is configured to detect an initial logic state of an input signal, and to generate, in response to the initial logic state, a first signal with a first logic state. The correction circuit is configured to compare the first signal having the first logic state with a second signal having a second logic state, and to generate an enable signal according to the comparison. The adjustment circuit is configured to be enabled by the enable signal when the first logic state of the first signal is different from the second logic state of the second signal, to generate an adjustment signal to the detection circuit, in which the detection circuit is further configured to be adjusted according to the adjustment signal, to generate an adjusted first signal.

The present disclosure provides a circuit. The circuit includes a detection circuit, a correction circuit and an adjustment circuit. The detection circuit is configured to detect an initial logic state of an input signal, and to generate, in response to the initial logic state, a first signal with a first logic state. The correction circuit is configured to compare the first signal having the first logic state with a second signal having a second logic state, and to generate an enable signal according to the comparison. The adjustment circuit is configured to be enabled by the enable signal when the first logic state of the first signal is different from the second logic state of the second signal, to generate an adjustment signal to the detection circuit, in which the detection circuit is further configured to be adjusted according to the adjustment signal, to generate an adjusted first signal.

The present invention discloses a unidirectional bit error correction method for a OTP ROM, comprising: applying error correction encoding to bit information and writing the bit information to the OTP ROM; during power-up initialization, converting hard bit information read out from the OTP ROM to soft bit information; during the power-up initialization, performing error correction decoding through a soft bit decoder. The advantages of the present invention include: utilizing otherwise temporarily idle decoding modules in the chip, without requiring additional hardware resource, while providing stronger error correction capability to the OTP ROM, improving the stability of chip applications, prolonging chip service life, and significantly reducing rejection rate in chip production.

The present invention discloses a unidirectional bit error correction method for a OTP ROM, comprising: applying error correction encoding to bit information and writing the bit information to the OTP ROM; during power-up initialization, converting hard bit information read out from the OTP ROM to soft bit information; during the power-up initialization, performing error correction decoding through a soft bit decoder. The advantages of the present invention include: utilizing otherwise temporarily idle decoding modules in the chip, without requiring additional hardware resource, while providing stronger error correction capability to the OTP ROM, improving the stability of chip applications, prolonging chip service life, and significantly reducing rejection rate in chip production.