A decoding method adopting an algorithm with weight-based adjusted parameters and a decoding system are provided. The decoding method is applied to a decoder. M×N low density parity check codes (LDPC codes) having N variable nodes and M check nodes are generated from input signals. In the decoding method, information of the variable nodes and the check nodes is initialized. The information passed from the variable nodes to the check nodes is formed after multiple iterations. After excluding a connection to be calculated, a product of the remaining connections between the variable nodes and the check nodes is calculated. Next, an estimated first minimum or an estimated second minimum can be calculated with multi-dimensional parameters. The information passed from the check nodes to the variable nodes can be updated for making a decision.

A decoding method adopting an algorithm with weight-based adjusted parameters and a decoding system are provided. The decoding method is applied to a decoder. M×N low density parity check codes (LDPC codes) having N variable nodes and M check nodes are generated from input signals. In the decoding method, information of the variable nodes and the check nodes is initialized. The information passed from the variable nodes to the check nodes is formed after multiple iterations. After excluding a connection to be calculated, a product of the remaining connections between the variable nodes and the check nodes is calculated. Next, an estimated first minimum or an estimated second minimum can be calculated with multi-dimensional parameters. The information passed from the check nodes to the variable nodes can be updated for making a decision.

Methods, systems, and devices for fixed weight codewords for ternary memory cells are described. A memory device may generate a codeword from a set of data bits and invert a portion of the codeword so that the codeword is associated with a target distribution of programmable states. After inverting the portion of the codeword, the memory device store the codeword in a set of ternary cells according to a coding scheme. The memory device may read the codeword from the set of ternary cells and select one or more reference voltages for the set of ternary cells based on the target distribution for the codeword and the states of the ternary cells.

A solution is proposed for error processing, wherein n byte error positions of n byte errors are predefined (where n is a positive integer), wherein this involves determining whether there is a further byte error position on the basis of the n byte error positions and on the basis of n + 1 error syndrome components of a first error code.

Methods, systems, and devices for fixed weight codewords for ternary memory cells are described. A memory device may generate a codeword from a set of data bits and invert a portion of the codeword so that the codeword is associated with a target distribution of programmable states. After inverting the portion of the codeword, the memory device store the codeword in a set of ternary cells according to a coding scheme. The memory device may read the codeword from the set of ternary cells and select one or more reference voltages for the set of ternary cells based on the target distribution for the codeword and the states of the ternary cells.

A binary encoder includes an input configured to receive a binary signal, an encoding processor configured to compute a plurality of different variations of the binary signal, combine each of the different variations with a different redundancy sequence to create a plurality of optional output binary sequences, and select one of the optional output binary sequences according to a binary digit prevalence, and an output configured to output the selected binary sequence. A decoder configured to identify a redundancy sequence of a received binary signal to select a transformation function according to the redundancy sequence and to convert the binary signal according to the transformation function.

A binary encoder includes an input configured to receive a binary signal, an encoding processor configured to compute a plurality of different variations of the binary signal, combine each of the different variations with a different redundancy sequence to create a plurality of optional output binary sequences, and select one of the optional output binary sequences according to a binary digit prevalence, and an output configured to output the selected binary sequence. A decoder configured to identify a redundancy sequence of a received binary signal to select a transformation function according to the redundancy sequence and to convert the binary signal according to the transformation function.

There is provided a method of transporting error correction codes (ECCs) in a transmission stream, the method including encoding a data stream from a data source into data symbols, generating first ECCs from the data symbols, encoding the first ECCs into first error correction code (ECC) symbols, merging the data symbols and the first ECC symbols into the transmission stream, the first ECC symbols being merged before the data symbols into the transmission stream, and transmitting the merged transmission stream to a sink device via a communication link, the first ECC symbols being transmitted before the data symbols.

There is provided a method of transporting error correction codes (ECCs) in a transmission stream, the method including encoding a data stream from a data source into data symbols, generating first ECCs from the data symbols, encoding the first ECCs into first error correction code (ECC) symbols, merging the data symbols and the first ECC symbols into the transmission stream, the first ECC symbols being merged before the data symbols into the transmission stream, and transmitting the merged transmission stream to a sink device via a communication link, the first ECC symbols being transmitted before the data symbols.

Bit-flip coding uses a bit-flip encoder to flip bits in a redundancy-intersecting vector of a binary array having n rows and n columns until Hamming weights of the binary array are within a predetermined range of n divided by two. Information bits of an input data word to the bit-flip coding apparatus are stored in locations within the binary array that are not occupied by n redundancy bits of a redundancy vector.