Data compression includes: inputting data comprising a vector that requires a first amount of memory; compressing the vector into a compressed representation while preserving information content of the vector, including: encoding, using one or more non-quantum processors, at least a portion of the vector to implement a quantum gate matrix; and modulating a reference vector using the quantum gate matrix to generate the compressed representation, wherein the compressed representation requires a second amount of memory that is less than the first amount of memory; and outputting the compressed representation to be displayed, stored, and/or further processed.

A decompression apparatus is provided. The decompression apparatus includes a memory configured to store compressed data decompressed and used in neural network processing of an artificial intelligence model, a decoder configured to include a plurality of logic circuits related to a compression method of the compressed data, decompress the compressed data through the plurality of logic circuits based on an input of the compressed data, and output the decompressed data, and a processor configured to obtain data of a neural network processible form from the data output from the decoder.

A method for compressing pre-compressed data used in a reconfigurable processor, where the pre-compressed data includes a number of data blocks, obtains a current data block, calculates a current checking code of the current data block, and compares the current checking code with an immediately-previous checking code. A tag of the current data block is marked as a first tag if the current checking code and the immediately-previous checking code are different, and is marked as a second tag if the current checking code and the immediately-previous checking code are the same. Only data blocks whose tags are the first tags are saved. A related device for compressing data, and a method and a device for decompressing data are also provided.

An apparatus for data storage includes an interface and a processor. The interface is configured to communicate with a memory device that includes (i) a plurality of memory cells and (ii) a data compression module. The processor is configured to determine a maximal number of errors that are required to be corrected by applying a soft decoding scheme to data retrieved from the memory cells, and based on the maximal number of errors, to determine an interval between multiple read thresholds for reading Code Words (CWs) stored in the memory cells for processing by the soft decoding scheme, so as to meet following conditions: (i) the soft decoding scheme achieves a specified decoding capability requirement, and (ii) a compression rate of the compression module when applied to confidence levels corresponding to readouts of the CWs, achieves a specified readout throughput requirement.

A transmission processing method includes: performing encoding or decoding, or instructing a second communication device to perform encoding or decoding. The encoding or decoding uses a multi-level structure.

A memory system includes a non-volatile memory and a controller. The controller is configured to, during a writing operation, generate a first error-detecting code from data that is input, perform a predetermined conversion on the data into first conversion data, generate a second error-detecting code from the first conversion data, and store the data, the first error-detecting code, and the second-error detecting code in the non-volatile memory. The controller is configured to during a read operation, read the data, the first error-detecting code, and the second error-detecting code from the non-volatile memory, perform a first error detection on the data using the first error-detecting code, perform the predetermined conversion on the data into second conversion data, perform a second error detection on the second conversion data using the second error-detecting code, and output the second conversion data based on results of the first and second error detections.

Disclosed is a network-based hyperdimensional system having an encoder configured to receive input data and encode the input data using hyperdimensional computing to generate a hypervector having encoded data bits that represent the input data. The network-based hyperdimensional system further includes a decoder configured to receive the encoded data bits, decode the encoded data bits, and reconstruct the input data from the decoded data bits. In some embodiments, the encoder is configured for direct hyperdimensional learning on transmitted data with no need for data decoding by the decoder.

An electronic apparatus is provided. The electronic apparatus includes a storage storing a matrix included in an artificial intelligence model, and a processor. The processor divides data included in at least a portion of the matrix by one of rows and columns of the matrix to form groups, clusters the groups into clusters based on data included in each of the groups, and quantizes data divided by the other one of rows and columns of the matrix among data included in each of the clusters.

One embodiment provides a system which facilitates data management. During operation, the system receives, by a first memory device, data to be written to a first non-volatile memory of the first memory device and to a second non-volatile memory of a storage drive distinct from the first memory device. The system performs, by the first memory device on the received data, a compression operation and erasure code (EC)-encoding to obtain a compressed EC codeword. The system initiates a first write operation and a second write operation in parallel, wherein the first write operation comprises writing a first part of the compressed EC codeword to the first non-volatile memory, and wherein the second write operation comprises writing the first part of the compressed EC codeword to the second non-volatile memory.

A packed error correction code (ECC) technique opportunistically embeds ECC check-bits with compressed data. When compressed, the data is encoded in fewer bits and is therefore fragmented when stored or transmitted compared with the uncompressed data. The ECC check-bits may be packed with compressed data at “source” points. The check-bits are transmitted along with the compressed data and, at any “intermediate” point between the source and a “destination” the check-bits may be used to detect and correct errors in the compressed data. In contrast with conventional systems, packed ECC enables end-to-end coverage for sufficiently-compressed data within the processor and also externally. While storage circuitry typically is protected by structure-specific ECC, protection is also beneficial for data as it is transmitted between processing and/or storage units.