Provided are a bit flipping device and method and a computer readable program for the same. The bit flipping device for input data having a two-dimensional array pattern includes: a clustering unit configured to generate at least one input data sequence based on the two-dimensional array pattern of the input data and classify the input data sequence into at least one cluster according to a preset method; and a bit flipping unit configured to perform bit flipping on erroneous bits in the input data sequence based on the classified cluster. Therefore, it is possible to further reduce inefficiency while further reducing system complexity compared to the existing error correction code-based bit flipping method by coupling the bit flipping device to an output side of a partial response maximum likelihood (PRML) detector to classify an output value of the PRML detector into at least one cluster and perform bit flipping based on the classified result.

Example systems, read channel circuits, data storage devices, and methods to provide signal correction based on soft information in a read channel are described. The read channel circuit includes a soft output detector, such as a soft output Viterbi algorithm (SOVA) detector, and a signal correction circuit. The soft output detector passes detected data bits and corresponding soft information to the signal correction circuit. The signal correction circuit uses the soft information to determine a signal correction value, which is combined with input signal to return a corrected signal to the soft output detector for a next iteration. In some configurations, the signal correction value may compensate for DC offset, AC coupling poles, and/or signal asymmetries to reduce baseline wander in the read channel.

The present invention is directed to communication systems and methods. In a specific embodiment, the present invention provides a receiver that includes an error correction module. A syndrome value, calculated based on received signals, may be used to enable the error correction module. The error correction module includes an error generator, a Nyquist error estimator, and a decoder. The decoder uses error estimation generated by the Nyquist error estimator to correct the decoded data. There are other embodiments as well.

The invention provides a signal processing device, including: an extraction section that extracts, from an input digital signal, a decoding target signal at an extraction timing that has been determined as a timing for extracting the decoding target signal; a decoding section that decodes the decoding target signal by estimating, by a maximum likelihood decoding, a candidate for a decoding result of the decoding target signal extracted by the extraction section and detecting a maximum likelihood decoding result; and an adjustment section that adjusts the extraction timing using a likelihood of the candidate for the decoding result estimated by the decoding section.

The present invention is directed to communication systems and methods. In a specific embodiment, the present invention provides a receiver that includes an error correction module. A syndrome value, calculated based on received signals, may be used to enable the error correction module. The error correction module includes an error generator, a Nyquist error estimator, and a decoder. The decoder uses error estimation generated by the Nyquist error estimator to correct the decoded data. There are other embodiments as well.

Provided are a bit flipping device and method and a computer readable program for the same. The bit flipping device for input data having a two-dimensional array pattern includes: a clustering unit configured to generate at least one input data sequence based on the two-dimensional array pattern of the input data and classify the input data sequence into at least one cluster according to a preset method; and a bit flipping unit configured to perform bit flipping on erroneous bits in the input data sequence based on the classified cluster. Therefore, it is possible to further reduce inefficiency while further reducing system complexity compared to the existing error correction code-based bit flipping method by coupling the bit flipping device to an output side of a partial response maximum likelihood (PRML) detector to classify an output value of the PRML detector into at least one cluster and perform bit flipping based on the classified result.

A deep neural network (DNN) media noise predictor configured for one-dimensional-magnetic (1DMR) recording or two-dimensional-magnetic (TDMR) is introduced. Such architectures are often combined with a trellis-based intersymbol interference (ISI) detection component in a turbo architecture to avoid the state explosion problem by separating the inter-symbol interference (ISI) detection and media noise estimation into two separate detectors and uses the turbo-principle to exchange information between them so as to address the modeling problem by way of training a DNN-based media noise estimators. Thus, beneficial aspects include a reduced bit-error rate (BER), an increased areal density, and a reduction in computational complexity and computational time.

Analog circuits are often non-linear, and the non-linearities can hurt performance. Designers would trade off power consumption to achieve better linearity. An efficient and effective calibration technique can address the non-linearities and reduce the overall power consumption. A dither signal injected to the analog circuit can be used to expose the non-linear behavior in the digital domain. To detect the non-linearities, a counting approach is applied to isolate non-linearities independent of the input distribution. The approach is superior to and different from other approaches in many ways.

Deterioration of convergence performance or operational stability due to an increase in constraint length is suppressed when coefficients are updated, so that decoding performance is improved. A decoding device according to the present technology includes an adaptive equalization unit that performs adaptive equalization, an adaptive maximum likelihood decoding unit that causes an identification point of maximum likelihood decoding to adaptively follow a characteristic of an input signal, a target waveform generation unit that, by convoluting a partial response coefficient into a decoded value, generates an equalization target waveform of the adaptive equalization which is performed by the adaptive equalization unit, an error signal generation unit that generates, as an equalization error signal, an error signal between the equalization target waveform and an equalized signal, and a coefficient updating unit that, through least-square-method computation for minimizing a correlation between the decoded value and the equalization error signal, updates the partial response coefficient which is used by the target waveform generation unit to generate the equalization target waveform.

An error recovery process provides for identifying a set of failed data blocks read from a storage medium during execution of a read command, populating sample buffers in a read channel with data of a first subset of the set of failed data blocks, and initiating an error recovery process on the data in the sample buffers. Responsive to successful recovery of one or more data blocks in the first subset, recovered data is released from the sample buffers and sample buffers locations previously-storing the recovered data are repopulated with data of a second subset of the set of failed data blocks. The error recovery process is then initiated on the data of the second subset of the failed data blocks while the error recovery process is ongoing with respect to data of the first subset of failed data blocks remaining in the sample buffers.