A quasi-cyclic LDPC coding and decoding method and apparatus, and an LDPC coder and decoder. The method includes: determining from a mother basis matrix set a basis matrix used for low density parity check (LDPC) coding (S202), wherein the basis matrix used for LDPC coding includes a first-type element and a second-type element, the first-type element corresponds to an all-zero square matrix, the second-type element corresponds to a matrix obtained by means of a cyclic shift of a unit matrix according to a value of the second-type element, and dimensions of the all-zero square matrix and the unit matrix are equal; and performing LDPC coding on an information sequence to be coded according to the basis matrix used for LDPC coding, and/or performing LDPC decoding on a data sequence to be decoded according to the basis matrix used for LDPC coding (S204).

Methods and apparatus associated with storing data in high or low energy zones are described. Example apparatus include a data storage system (DSS) that protects a message using an erasure code (EC). A location in the DSS may have an energy efficiency rating or a latency. Example apparatus include circuits that produce EC encoded data that has a likelihood of use, that select a location to store the EC encoded data in the DSS based on the energy efficiency rating, the latency, or the likelihood of use, that store the EC encoded data in the location, and that compute an order of retrieval for EC encoded data stored in the location. The order of retrieval may be based on the energy efficiency rating or the latency. The EC encoded data may also have a priority based on the number of erasures for which the EC corrects.

A quasi-cyclic LDPC coding and decoding method and apparatus, and an LDPC coder and decoder. The method includes: determining from a mother basis matrix set a basis matrix used for low density parity check (LDPC) coding (S202), wherein the basis matrix used for LDPC coding includes a first-type element and a second-type element, the first-type element corresponds to an all-zero square matrix, the second-type element corresponds to a matrix obtained by means of a cyclic shift of a unit matrix according to a value of the second-type element, and dimensions of the all-zero square matrix and the unit matrix are equal; and performing LDPC coding on an information sequence to be coded according to the basis matrix used for LDPC coding, and/or performing LDPC decoding on a data sequence to be decoded according to the basis matrix used for LDPC coding (S204).

A quasi-cyclic LDPC coding and decoding method and apparatus, and an LDPC coder and decoder. The method includes: determining from a mother basis matrix set a basis matrix used for low density parity check (LDPC) coding (S202), wherein the basis matrix used for LDPC coding includes a first-type element and a second-type element, the first-type element corresponds to an all-zero square matrix, the second-type element corresponds to a matrix obtained by means of a cyclic shift of a unit matrix according to a value of the second-type element, and dimensions of the all-zero square matrix and the unit matrix are equal; and performing LDPC coding on an information sequence to be coded according to the basis matrix used for LDPC coding, and/or performing LDPC decoding on a data sequence to be decoded according to the basis matrix used for LDPC coding (S204).

Certain aspects of the present disclosure provide techniques and apparatus for low density parity check (LDPC) interleaving with improved error floor performance. A method for wireless communications that may be provided by a transmitting device is provided. The method generally includes encoding one or more information bits using a LDPC code to produce a coded bit sequence comprising systematic bits and parity bits. The transmitting device stores the coded bit sequence in a circular buffer. The transmitting device performs rate matching on the coded bit sequence. The rate matching includes interleaving the parity bits with a partial interleaver and interleaving the systematic bits and interleaved parity bits with a systematic bit priority mapping (SBPM) interleaver. The transmitting device maps the SBPM interleaved bit sequence to constellation points according to a modulation scheme and transmits the modulated bit sequence.

Certain aspects of the present disclosure provide techniques and apparatus for low density parity check (LDPC) interleaving with improved error floor performance. A method for wireless communications that may be provided by a transmitting device is provided. The method generally includes encoding one or more information bits using a LDPC code to produce a coded bit sequence comprising systematic bits and parity bits. The transmitting device stores the coded bit sequence in a circular buffer. The transmitting device performs rate matching on the coded bit sequence. The rate matching includes interleaving the parity bits with a partial interleaver and interleaving the systematic bits and interleaved parity bits with a systematic bit priority mapping (SBPM) interleaver. The transmitting device maps the SBPM interleaved bit sequence to constellation points according to a modulation scheme and transmits the modulated bit sequence.

A quasi-cyclic LDPC coding and decoding method and apparatus, and an LDPC coder and decoder. The method includes: determining from a mother basis matrix set a basis matrix used for low density parity check (LDPC) coding (S202), wherein the basis matrix used for LDPC coding includes a first-type element and a second-type element, the first-type element corresponds to an all-zero square matrix, the second-type element corresponds to a matrix obtained by means of a cyclic shift of a unit matrix according to a value of the second-type element, and dimensions of the all-zero square matrix and the unit matrix are equal; and performing LDPC coding on an information sequence to be coded according to the basis matrix used for LDPC coding, and/or performing LDPC decoding on a data sequence to be decoded according to the basis matrix used for LDPC coding (S204).

Methods and apparatus associated with data cold storage are described. Example apparatus include an array of data storage devices arranged in rows and columns. Columns of the array are orthogonal to rows. A row has an associated row-centric power supply, and a column has an associated column-centric local electronics module (LEM) that controls a data storage device in the column independently of other data storage devices in the array. Example apparatus include logics that control a power mode of a data storage device independently of other data storage devices in the array, that control a power mode of an LEM, that adaptively regulate the level of data stored in a buffer, and that determine whether a data object will be stored in the buffer or stored on a data storage device in the array, based on the probability the data object will be accessed within a threshold period of time.

Methods and apparatus associated with storing data in high or low energy zones are described. Example apparatus include a data storage system (DSS) that protects a message using an erasure code (EC). A location in the DSS may have an energy efficiency rating or a latency. Example apparatus include logics that produce an EC that has a likelihood of use, that select a location to store the EC in the DSS based on the energy efficiency rating, the latency, or the likelihood of use, that store the EC in the location, and that compute an order of retrieval for an EC stored in the location. The order of retrieval may be based on the energy efficiency rating or the latency. The EC may also have a priority based on the number of erasures for which the EC corrects.

Methods and apparatus associated with data cold storage are described. Example apparatus include an array of data storage devices arranged in rows and columns. Columns of the array are orthogonal to rows. A row has an associated row-centric power supply, and a column has an associated column-centric local electronics module (LEM) that controls a data storage device in the column independently of other data storage devices in the array. Example apparatus include logics that control a power mode of a data storage device independently of other data storage devices in the array, that control a power mode of an LEM, that adaptively regulate the level of data stored in a buffer, and that determine whether a data object will be stored in the buffer or stored on a data storage device in the array, based on the probability the data object will be accessed within a threshold period of time.