In general, according to an embodiment, a memory system includes a memory device including a memory cell; and a controller. The controller is configured to: receive first data from the memory cell in a first data reading; receive second data from the memory cell in a second data reading that is different from the first data reading; convert a first value that is based on the first data and the second data, to a second value in accordance with a first relationship; and convert the first value to a third value in accordance with a second relationship that is different from the first relationship.

In general, according to an embodiment, a memory system includes a memory device including a memory cell; and a controller. The controller is configured to: receive first data from the memory cell in a first data reading; receive second data from the memory cell in a second data reading that is different from the first data reading; convert a first value that is based on the first data and the second data, to a second value in accordance with a first relationship; and convert the first value to a third value in accordance with a second relationship that is different from the first relationship.

Systems and methods are disclosed that relate to performing rate matching when using polar codes. In one embodiment, a plurality of bits are received at a polar encoder. A value is obtained that corresponds to at least one of: a coding rate to be used to transmit the plurality of bits, and a number of coded bits to be used to transmit the plurality of bits. It is determined which range of values the value falls within, and an information sequence is obtained that corresponds to the range the value falls within. The plurality of bits are mapped to a subset of positions of an input vector according to the information sequence. The remaining positions of the input vector are set as frozen values that are known by a decoder. The input vector is then encoded in the polar encoder to generate a codeword.

Certain aspects of the present disclosure generally relate to techniques for puncturing of structured low-density parity-check (LDPC) codes. Certain aspects of the present disclosure generally relate to methods and apparatus for a high-performance, flexible, and compact LDPC code. Certain aspects can enable LDPC code designs to support large ranges of rates, blocklengths, and granularity, while being capable of fine incremental redundancy hybrid automatic repeat request (IR-HARQ) extension while maintaining good floor performance, a high-level of parallelism to deliver high throughout performance, and a low description complexity.

A time de-interleaving circuit and a time de-interleaving method perform a time de-interleaving process through writing and reading a plurality of sets of time interleaved data into and from a first memory and a second memory. The time de-interleaving method includes: selecting a set of first time interleaved data and a set of second time interleaved data from the plurality of sets of time interleaved data, the set of first time interleaved data and the set of second time interleaved data having the same delay length; writing the set of first time interleaved data into the first memory; and writing the set of second time interleaved data into the second memory. The first memory utilizes a bit length as an access unit, and the second memory has an access unit smaller than the bit width.

Certain aspects of the present disclosure generally relate to techniques for puncturing of structured low-density parity-check (LDPC) codes. Certain aspects of the present disclosure generally relate to methods and apparatus for a high-performance, flexible, and compact LDPC code. Certain aspects can enable LDPC code designs to support large ranges of rates, blocklengths, and granularity, while being capable of fine incremental redundancy hybrid automatic repeat request (IR-HARQ) extension while maintaining good floor performance, a high-level of parallelism to deliver high throughout performance, and a low description complexity.

This invention presents a method and the corresponding hardware apparatus for decoding LDPC codes using a vertical layered (VL) iterative message passing algorithm. The invention operates on quasi-cyclic LDPC (QC-LDPC) codes, for which the non-zero circulant permutation matrices (CPMs) are placed at specific locations in the parity-check matrix of the codes, forming concentrated clusters of CPMs. The purpose of the invention is to take advantage of the organization of CPMs in clusters in order to derive a specific hardware architecture, consuming less power than the classical VL decoders. This is achieved by minimizing the number of read and write accesses to the main memories of the design.

A detection circuit performs a turbo detection process to recover a frame of data symbols from a received signal, the data symbols of the frame having been effected, during transmission, by a Markov process with the effect that the data symbols of the frame in the received signal are dependent one or more preceding data symbols which can be represented as a trellis having a plurality of trellis stages. The detection circuit comprises a plurality of processing elements, each of the processing elements is associated with one of the trellis stages representing the dependency of the data symbols of the frame according to the Markov process and each of the processing elements is configured to receive one or more soft decision values corresponding to one or more data symbols associated with the trellis stage, and each of one or more of the processing elements is configured, in one clock cycle to receive fixed point data representing a priori forward state metrics a priori backward state metrics, and fixed point data representing a priori soft decision values for the one or more data symbols being detected for the trellis stage. For each of a plurality of clock cycles of the turbo detection process, the detection circuit is configured to process, for each of the processing elements representing the trellis stages, the a priori information for the one or more data symbols being detected for the trellis stage associated with the processing element, and to provide the extrinsic soft decision values corresponding to the one or more data symbols for a next clock cycle of the turbo detection process.

Systems and method relating generally to solid state memory, and more particularly to systems and methods for recycling data in a solid state memory. The systems and methods include receiving a data set maintained in a memory device, applying at least one iteration of a data decoding algorithm to the data set by a data decoder circuit to yield a decoded output, counting the number of iterations of the data decoding algorithm applied to the data set to yield an iteration count, and recycling the data set to the memory device. The recycling is triggered based at least in part on the iteration count.

A system, method and program product that utilizes a hybrid fault tolerance system for managing data. A system is disclosed that includes: a system for partitioning memory into a set of partitions that includes a designated partition for storing immutable objects; a write system for storing an immutable object in the designated partition, wherein the immutable object is coded with a hardware-based fault tolerance system to generate a set of hardware-based codewords, and wherein the immutable object is further coded with a software-based fault tolerance system to generate a set of software-based codewords; a read system for retrieving the immutable object, wherein the read system decodes each hardware-based codeword for the immutable object, and in response to a failed decoding of a hardware-based codeword, the read system decodes the software-based codeword containing a failed hardware-based codeword.