H03M13/6544

ANALOG FORWARD ERROR CORRECTION

A wireless communication device, including a radiofrequency frontend, configured to wirelessly receive a radiofrequency signal; perform one or more analog baseband operations on the received radiofrequency signal, according to a radio access technology; and output an analog signal representing an output of the analog baseband operations on the received radiofrequency signal; an error corrector, configured to perform an error correction operation on the analog signal; and output an error corrected signal in analog domain; and the analog-digital converter, configured to convert the error corrected signal to digital domain.

Apparatus and method for transmitting and receiving a quasi-cyclic low density parity check code in a multimedia communication system

A method and apparatus are provided for transmitting an LDPC code in a multimedia system. The method includes generating an LDPC code based on a resulting parity check matrix which is generated by performing a row splitting operation on a base parity check matrix; and transmitting the LDPC code. The row splitting operation includes splitting each row block included in the base parity check matrix into row blocks, a number of the row blocks is determined based on a splitting factor, and the splitting factor is determined based on a number of repair symbols included in a repair symbol block of the base parity check matrix, a number of rows included in the base parity check matrix, and a scaling factor for determining a size of each permutation matrix in the resulting parity check matrix and a size of each zero matrix included in the resulting parity check matrix.

FULLY PARALLEL TURBO DECODING
20170244427 · 2017-08-24 ·

A detection circuit performs a turbo detection process to recover a frame of data symbols from a received signal, the data symbols of the frame having been effected, during transmission, by a Markov process with the effect that the data symbols of the frame in the received signal are dependent one or more preceding data symbols which can be represented as a trellis having a plurality of trellis stages. The detection circuit comprises a plurality of processing elements, each of the processing elements is associated with one of the trellis stages representing the dependency of the data symbols of the frame according to the Markov process and each of the processing elements is configured to receive one or more soft decision values corresponding to one or more data symbols associated with the trellis stage, and each of one or more of the processing elements is configured, in one clock cycle to receive fixed point data representing a priori forward state metrics a priori backward state metrics, and fixed point data representing a priori soft decision values for the one or more data symbols being detected for the trellis stage. For each of a plurality of clock cycles of the turbo detection process, the detection circuit is configured to process, for each of the processing elements representing the trellis stages, the a priori information for the one or more data symbols being detected for the trellis stage associated with the processing element, and to provide the extrinsic soft decision values corresponding to the one or more data symbols for a next clock cycle of the turbo detection process.

METHOD AND APPARATUS FOR PERFORMING ENCODING ON BASIS OF PARITY CHECK MATRIX OF LOW DENSITY PARITY CHECK CODE GENERATED FROM PROTOGRAPH IN WIRELESS COMMUNICATION SYSTEM
20220271776 · 2022-08-25 ·

A method for performing low density parity check (LDPC) coding of a transmitter in a wireless communication system, according to the present disclosure, may comprise the steps of: acquiring a proto-matrix corresponding to a protograph; on the basis of weights and lifting factors of columns of the proto-matrix, acquiring one or more permuted vectors corresponding to each of the columns, a first permuted vector included in the one or more permuted vectors having been randomly generated; distributing the one or more permuted vectors for each row of a corresponding column; on the basis of the distributed one or more permuted vectors, acquiring a plurality of lifted sub matrices corresponding to a plurality of elements of the proto-matrix; generating a base graph on the basis of the plurality of lifted sub matrices; generating a parity check matrix (PCM) on the basis of the base graph; and performing LDPC coding by using the PCM.

Variable rate low density parity check decoder

A method includes receiving a first data frame and a second data frame from a communication channel; decoding the first data frame using a first portion of an extended parity-check matrix (PCM); and decoding the second data frame using a second portion of the extended PCM. The first portion is a subset of the second portion.

Base parity-check matrices for LDPC codes that have subsets of orthogonal rows

Protograph-based LDPC codes are obtained from z-row-orthogonal base matrices with some additional structure constraints, such as a diagonal and/or double-diagonal structure, in order to allow a high parallelization that is a multiple of z, while having an efficient encoding or decoding. A “big” base matrix is constructed from a structured square submatrix in order to have a WiMAX-like structure and a z-row-orthogonality. Also, starting from a “smaller” base matrix having a part arranged in a double-diagonal shape with tail-biting one, an expansion by a factor equal to z can be performed, followed by an addition of a single one-entry into the last column at a specific location, thereby obtaining a three-degree column, and followed by a row and/or column permutation in order to obtain a base matrix in a WiMAX-like structure.

Method and apparatus for performing encoding on basis of parity check matrix of low density parity check code generated from protograph in wireless communication system
11784663 · 2023-10-10 · ·

A method for performing low density parity check (LDPC) coding of a transmitter in a wireless communication system, according to the present disclosure, may comprise the steps of: acquiring a proto-matrix corresponding to a protograph; on the basis of weights and lifting factors of columns of the proto-matrix, acquiring one or more permuted vectors corresponding to each of the columns, a first permuted vector included in the one or more permuted vectors having been randomly generated; distributing the one or more permuted vectors for each row of a corresponding column; on the basis of the distributed one or more permuted vectors, acquiring a plurality of lifted sub matrices corresponding to a plurality of elements of the proto-matrix; generating a base graph on the basis of the plurality of lifted sub matrices; generating a parity check matrix (PCM) on the basis of the base graph; and performing LDPC coding by using the PCM.

VARIABLE RATE LOW DENSITY PARITY CHECK DECODER

A method includes receiving a first data frame and a second data frame from a communication channel; decoding the first data frame using a first portion of an extended parity-check matrix (PCM); and decoding the second data frame using a second portion of the extended PCM. The first portion is a subset of the second portion.

DESIGN OF BASE PARITY-CHECK MATRICES FOR LDPC CODES THAT HAVE SUBSETS OF ORTHOGONAL ROWS

Protograph-based LDPC codes are obtained from z-row-orthogonal base matrices with some additional structure constraints, such as a diagonal and/or double-diagonal structure, in order to allow a high parallelization that is a multiple of z, while having an efficient encoding or decoding. A big base matrix is constructed from a structured square submatrix in order to have a WiMAX-like structure and a z-row-orthogonality. Also, starting from a smaller base matrix having a part arranged in a double-diagonal shape with tail-biting one, an expansion by a factor equal to z can be performed, followed by an addition of a single one-entry into the last column at a specific location, thereby obtaining a three-degree column, and followed by a row and/or column permutation in order to obtain a base matrix in a WiMAX-like structure.

Fully parallel turbo decoding

A circuit performs a turbo detection process recovering data symbols from a received signal effected, during transmission, by a Markov process with effect that the data symbols are dependent on preceding data symbols represented as a trellis having a plurality of trellis stages. The circuit comprises processing elements, associated with trellis stages representing these dependencies and each configured to receive soft decision values corresponding to associated data symbols Each processing element configured, in one clock cycle to receive data representing a priori forward and backward state metrics, and a priori soft decision values for data symbols detected for the trellis stage. For each clock cycle of the turbo detection process, the circuit processes, for processing elements representing the trellis stages, the a priori information for associated data symbols detected for the trellis stage, and to provide extrinsic soft decision values corresponding to data symbols for a next clock cycle.