An image sensing device may include one or more compression modules that compress digitized pixel reset values obtained from light sensing elements. The device may perform a CDS operation in which the compressed reset values are stored, decompressed, and then subtracted from light dependent values obtained from the light sensing elements. The compressed reset values may also be output from the device without CDS subtraction having been performed. The light dependent values may also be compressed. CDS corrected output pixel values may also be compressed.

Devices and methods that aim to improve flicker noise rejection in switched-capacitor (SC) integrators are disclosed. An example SC integrator includes a first and a second sampling capacitors, an amplifier, an integrating capacitor, coupled at least to an output of the amplifier, and a switching arrangement. By adding (i.e., integrating in the integrating capacitor) sign-inverted samples of a flicker noise of the amplifier at every clock cycle of a master clock and by keeping the time distance/delay between those samples relatively small regardless of the master clock frequency, such a SC integrator may provide improvements in terms of rejecting the flicker noise of the amplifier.

Disclosed are a readout circuit, a signal quantizing method, a signal quantizing device, and a computer device. The readout circuit includes: a signal sampler, including a plurality of channels; a plurality of integrators, connected to the plurality of channels and having a one-to-one releationship with the plurality of channels; a signal processor, including a first operational amplifier, a sampling input of the first operational amplifier being connected to outputs of the plurality of integrators, respectively; and an analog-digital converter. An input of the analog-digital converter is connected to an output of the first operational amplifier.

An amplification apparatus includes an amplifier having an inverting terminal, and a non-inverting terminal connected to a reset voltage node, a first capacitor connected to the inverting terminal, an input voltage being applied to the first capacitor, a second capacitor connected to the inverting terminal and an output terminal of the amplifier, and a duty-cycled resistor, connected in parallel to the second capacitor, including a first resistor. The duty-cycled resistor is configured to connect the first resistor and the inverting terminal and to disconnect the first resistor and the reset voltage node during a first time interval included in a period to complete an on-and-off cycle of the duty-cycled resistor, and disconnect the first resistor and the inverting terminal and to connect the first resistor and the reset voltage node during a second time interval included in the period.

A switched-capacitor delta-sigma data converter circuit includes compensation for voltage reference error that may cause non-linearity and inter-channel crosstalk. The circuit includes a voltage reference circuit, an integrator, a quantizer that quantizes the output of the integrator and a reference feedback switched-capacitor network that provides feedback charge quanta to the integrator that represents an output of the quantizer, so that the output of the quantizer, on average, represents an input signal provided to the integrator. In addition, a compensation switched-capacitor network is included for drawing dummy load charge quanta from the voltage reference output that is not provided to the integrator so that a total charge drawn from the voltage reference output when the reference feedback switched-capacitor network is coupled to the voltage reference output does not vary as the input voltage varies.

An analog-to-digital converter includes: a sample/hold circuit, which samples an analog signal, and outputs a first voltage; a digital-to-analog conversion circuit, which converts a digital signal to output a second voltage; an amplifier, which amplifies the first voltage and the second voltage; a noise shaping filter, which integrates a residual voltage corresponding to a difference between the amplified first voltage and the amplified second voltage, and generates a first integration voltage and a second integration voltage; a comparator, which compares a sum of the amplified first voltage, the first integration voltage, and the second integration voltage with the amplified second voltage; and a SAR logic, which outputs the digital signal according to a comparison result of the comparator, and controls the digital-to-analog conversion circuit.

An A/D converter includes: a sampler that includes a sampling capacitor and samples an input signal; a D/A converter that selectively outputs an analog voltage; an integrator that integrates an input from the sampler and an input from the D/A converter; Multiple switches that include a first switch independently connecting the sampler to the integrator, a second switch independently connecting the D/A converter to the integrator, a third switch, and, a fourth switch, a quantizer that quantizes an output of the integrator; a control circuit that outputs a digital value based on an output of the quantizer, and a reference potential generation circuit that provides a second reference potential to an integrator side of the sampler through the third switch and provides a first reference potential to the integrator side of the D/A converter through the fourth switch.

A delta-sigma modulator generates a bit stream signal from an analog signal by operating according to a modulation period including a sampling period and a filtering period and includes a digital-to-analog converter (DAC) configured to generate a charge signal according to one of a first reference voltage and a second reference voltage according to the bit stream signal during the sampling period and to output a signal generated according to the charge signal and the other of the first reference voltage and the second reference voltage; a loop filter configured to charge a sampling signal corresponding to the analog signal during the sampling period and to filter an output from the DAC and a signal generated according to the sampling signal during the filtering period; and a quantizer configured to generate the bit stream signal according to an output from the loop filter in the modulation period.

An A/D converter includes: a sampler that includes a sampling capacitor and samples an input signal; a D/A converter that selectively outputs an analog voltage; an integrator that integrates an input from the sampler and an input from the D/A converter; Multiple switches that include a first switch independently connecting the sampler to the integrator, a second switch independently connecting the D/A converter to the integrator, a third switch, and, a fourth switch, a quantizer that quantizes an output of the integrator; a control circuit that outputs a digital value based on an output of the quantizer, and a reference potential generation circuit that provides a second reference potential to an integrator side of the sampler through the third switch and provides a first reference potential to the integrator side of the D/A converter through the fourth switch.

A delta-sigma modulator generates a bitstream signal from a differential input signal including a first input signal and a second input signal by repeating a first operation and a second operation alternately. The delta-sigma modulator includes a first sampling capacitor, a second sampling capacitor, a third sampling capacitor, a fourth sampling capacitor, an operational amplifier, a first feedback capacitor, a second feedback capacitor, and a quantizer.