Provided is a modulation circuit that can correct an output state in real time and reliably modulate an input signal to output the modulated signal. The signal modulation circuit includes a subtractor, an integrator, a chopper circuit, a frequency divider, and a D-type flip-flop. A delay circuit of a sigma delta modulation circuit is not provided to a feedback circuit, and a signal is delayed and quantized in the D-type flip-flop. The chopper circuit inserts a zero level at timing synchronized with a clock signal, so that pulse density modulation is performed.

A delay chain circuit with series coupled delay elements receives a reference clock signal and outputs phase-shifted clock signals. A multiplexer circuit receives the phase-shifted clock signals and selects among the phase-shifted clock signals for output as in response to a selection signal. The selection signal is generated by a control circuit from a periodic signal having a triangular wave profile. A sigma-delta modulator converts the periodic signal to a digital signal, and an integrator circuit integrates the digital signal to output the selection signal. The selected phase-shifted clock signal is applied as the reference signal to a phase locked loop which generates a spread spectrum clock signal.

A frequency ratio measurement device includes a counter section configured to count a time event of a first signal and output a count value obtained by multiplying the time event by k.sub.0, a time to digital converter section configured to output a time digital value corresponding to a phase difference between the first signal and a second signal, a combiner section configured to output a combined value of the count value and the time digital value, a subtractor section configured to output a difference value between a first value based on the combined value and a second value, a quantizer section configured to compare a third value based on the difference value with a predetermined threshold to thereby output a quantized value obtained by quantizing the third value, and a feedback section configured to output, based on a time event of the second signal, the second value based on the quantized value. The frequency ratio measurement device outputs, based on the quantized value, a delta-sigma modulated signal corresponding to a frequency ratio of the first signal and the second signal.

A delay chain circuit with series coupled delay elements receives a reference clock signal and outputs phase-shifted clock signals. A multiplexer circuit receives the phase-shifted clock signals and selects among the phase-shifted clock signals for output as in response to a selection signal. The selection signal is generated by a control circuit from a periodic signal having a triangular wave profile. A sigma-delta modulator converts the periodic signal to a digital signal, and an integrator circuit integrates the digital signal to output the selection signal. The selected phase-shifted clock signal is applied as the reference signal to a phase locked loop which generates a spread spectrum clock signal.

An analog-to-digital converter (ADC) includes a first operator configured to subtract an analog value from an analog signal; an amplifier configured to amplify an output of the first selector; a filter configured to filter an output of the amplifier; a quantizer configured to generate a digital bit stream from an output of the filter; and a digital-to-analog converter (DAC) configured to output the analog value according to the digital bit stream.

A frequency ratio measurement device includes a counter section configured to count a time event of a first signal and output a count value obtained by multiplying the time event by k.sub.0, a time to digital converter section configured to output a time digital value corresponding to a phase difference between the first signal and a second signal, a combiner section configured to output a combined value of the count value and the time digital value, a subtractor section configured to output a difference value between a first value based on the combined value and a second value, a quantizer section configured to compare a third value based on the difference value with a predetermined threshold to thereby output a quantized value obtained by quantizing the third value, and a feedback section configured to output, based on a time event of the second signal, the second value based on the quantized value. The frequency ratio measurement device outputs, based on the quantized value, a delta-sigma modulated signal corresponding to a frequency ratio of the first signal and the second signal.

Improved switching techniques for controlling three-level current steering DAC cells are disclosed. The techniques include decoupling two current sources, implemented as field-effect transistors (FETs), of a DAC cell both from their respective bias sources and from a load for converting a zero digital input, where the decoupling is performed in a certain order. The techniques also include coupling the current sources to their respective bias sources and to the load for converting a non-zero digital input, where the coupling is also performed in a certain order. The certain order of decoupling and coupling the bias sources and the load to the current sources of a DAC cell are based on the phenomenon of current memory in FETs. Utilizing current memory when operating a DAC cell may allow reducing power consumption while preserving the high performance properties of a three-level current steering DAC.

Method and apparatus for nonlinear signal processing include mitigation of outlier noise in the process of analog-to-digital conversion and adaptive real-time signal conditioning, processing, analysis, quantification, comparison, and control. Methods, processes and apparatus for real-time measuring and analysis of variables include statistical analysis and generic measurement systems and processes which are not specially adapted for any specific variables, or to one particular environment. Methods and corresponding apparatus for mitigation of electromagnetic interference, for improving properties of electronic devices, and for improving and/or enabling coexistence of a plurality of electronic devices include post-processing analysis of measured variables and post-processing statistical analysis. Methods, processes and apparatus for secure communications include low-power communications and physical-layer steganography.

A digital delta-sigma modulator may include a loop filter having a loop filter input configured to receive an input signal and generate an intermediate signal responsive to the input signal and a multi-bit quantizer configured to quantize the intermediate signal into a quantized output signal which is fed back as an input to the loop filter. The multi-bit quantizer may further be configured to operate in at least two modes comprising: (a) a normal mode in which, for each sample of the intermediate signal, the multi-bit quantizer generates a corresponding sample having a value selected from a set of a plurality of quantization levels; and (b) a code suppression mode in which, for each sample of the intermediate signal, the multi-bit quantizer generates a corresponding sample having a value selected from a subset of the set of a plurality of quantization levels.

An analog-to-digital converter (ADC) includes a first operator configured to subtract an analog value from an analog signal; an amplifier configured to amplify an output of the first selector; a filter configured to filter an output of the amplifier; a quantizer configured to generate a digital bit stream from an output of the filter; and a digital-to-analog converter (DAC) configured to output the analog value according to the digital bit stream.