What is provided is a subtractor, as a re-quantization device, which is configured to detect re-quantization noise, a discrete time filter which is configured to perform frequency weighting on the detected re-quantization noise, an adder which is configured to add an additional signal to quantization noise, and an additional signal selector which is configured to select a value at the present time of a column of an additional signal for minimizing the magnitude of quantization noise having been subjected to frequency weighting evaluated one sampling or more later.

What is provided is a subtractor, as a re-quantization device, which is configured to detect re-quantization noise, a discrete time filter which is configured to perform frequency weighting on the detected re-quantization noise, an adder which is configured to add an additional signal to quantization noise, and an additional signal selector which is configured to select a value at the present time of a column of an additional signal for minimizing the magnitude of quantization noise having been subjected to frequency weighting evaluated one sampling or more later.

Described herein is a method and apparatus for reducing ISI in a single-bit modulator without reducing the dynamic range of the modulator. In one embodiment, the signal fed back to the input of the modulator is not the single-bit outputs of a quantizer as in the prior art, but rather patterns of such outputs. The patterns are selected so that each pattern has the same number of transition edges and there is thus no mismatch of transition times. In one embodiment, the patterns are created by digital logic. In another embodiment, an analog signal is added to the error signal in the feedback loop which causes the quantizer to generate the patterns. When the amplitude of the input signal exceeds a certain level, the modulator reverts to the typical operation of a prior art modulator, thus preserving the full dynamic range of the modulator.

Described herein is a method and apparatus for reducing ISI in a single-bit modulator without reducing the dynamic range of the modulator. In one embodiment, the signal fed back to the input of the modulator is not the single-bit outputs of a quantizer as in the prior art, but rather patterns of such outputs. The patterns are selected so that each pattern has the same number of transition edges and there is thus no mismatch of transition times. In one embodiment, the patterns are created by digital logic. In another embodiment, an analog signal is added to the error signal in the feedback loop which causes the quantizer to generate the patterns. When the amplitude of the input signal exceeds a certain level, the modulator reverts to the typical operation of a prior art modulator, thus preserving the full dynamic range of the modulator.

The pulse width modulator includes a subtraction unit configured to perform subtraction between an m value digital signal and a pulse width modulation signal; a feedforward filter unit configured such that a modulator to which an output signal of the subtraction unit is input and which includes integrators of a second order or higher is in cascade connection, and configured to operate with a sampling frequency FS; a product-sum computing unit configured to operate with a sampling frequency (FS/n) (n: an integer of two or more) to perform product-sum computing of an output signal of each integrator of the feedforward filter unit; and a pulse width modulation unit configured to operate with the sampling frequency (FS/n) to perform pulse width modulation of an output signal of the product-sum computing unit to output a pulse width modulation signal.

The pulse width modulator includes a subtraction unit configured to perform subtraction between an m value digital signal and a pulse width modulation signal; a feedforward filter unit configured such that a modulator to which an output signal of the subtraction unit is input and which includes integrators of a second order or higher is in cascade connection, and configured to operate with a sampling frequency FS; a product-sum computing unit configured to operate with a sampling frequency (FS/n) (n: an integer of two or more) to perform product-sum computing of an output signal of each integrator of the feedforward filter unit; and a pulse width modulation unit configured to operate with the sampling frequency (FS/n) to perform pulse width modulation of an output signal of the product-sum computing unit to output a pulse width modulation signal.