A delta-sigma Analog-to-Digital Converter (ADC) (IC) which includes an input feed-forward path extending from an input to the ADC to a feed-forward summing circuit disposed between a loop filter and quantizer of the ADC, and a filter disposed in the feed-forward path as an apparatus for improving distortion performance in the delta-sigma ADC. The filter may be a low pass filter, for example, a Resistor-Capacitor (RC) circuit. The filter may have a cut-off frequency outside the ADC's passband. The filtering provided may be continuous-time filtering, even if the delta-sigma ADC is a discrete-time delta-sigma ADC.

Devices and methods that aim to improve flicker noise rejection in switched-capacitor (SC) integrators are disclosed. An example SC integrator includes a first and a second sampling capacitors, an amplifier, an integrating capacitor, coupled at least to an output of the amplifier, and a switching arrangement. By adding (i.e., integrating in the integrating capacitor) sign-inverted samples of a flicker noise of the amplifier at every clock cycle of a master clock and by keeping the time distance/delay between those samples relatively small regardless of the master clock frequency, such a SC integrator may provide improvements in terms of rejecting the flicker noise of the amplifier.

Exemplary multipath digital microphone described herein can comprise exemplary embodiments of adaptive ADC range multipath digital microphones, which allow low power to be achieved for amplifiers or gain stages, as well as for exemplary adaptive ADCs in exemplary multipath digital microphone arrangements described herein, while still providing a high DR digital microphone systems. Further non-limiting embodiments can comprise an exemplary glitch removal component configured to minimize audible artifacts associated with the change in the gain of the exemplary adaptive ADCs.

A motion sensor with sigma-delta analog-to-digital converter (ADC) having improved bias instability is presented herein. Differential outputs of a differential amplifier of the sigma-delta ADC are electrically coupled, via respective capacitances, to differential inputs of the differential amplifier. To minimize bias instability corresponding to flicker noise that has been injected into the differential inputs, the differential inputs are electrically coupled, via respective pairs of electronic switches, to feedback resistances based on a pair of switch control signals. In this regard, a first feedback resistance of the feedback resistances is electrically coupled to a first defined voltage, and a second feedback resistance of the feedback resistances is electrically coupled to a second defined reference voltage. The differential outputs are electrically coupled to differential inputs of a differential comparator of the sigma-delta ADC, and complementary outputs of the differential comparator comprise the pair of switch control signals.

A switched-capacitor delta-sigma data converter circuit includes compensation for voltage reference error that may cause non-linearity and inter-channel crosstalk. The circuit includes a voltage reference circuit, an integrator, a quantizer that quantizes the output of the integrator and a reference feedback switched-capacitor network that provides feedback charge quanta to the integrator that represents an output of the quantizer, so that the output of the quantizer, on average, represents an input signal provided to the integrator. In addition, a compensation switched-capacitor network is included for drawing dummy load charge quanta from the voltage reference output that is not provided to the integrator so that a total charge drawn from the voltage reference output when the reference feedback switched-capacitor network is coupled to the voltage reference output does not vary as the input voltage varies.

Exemplary multipath digital microphone described herein can comprise exemplary embodiments of adaptive ADC range multipath digital microphones, which allow low power to be achieved for amplifiers or gain stages, as well as for exemplary adaptive ADCs in exemplary multipath digital microphone arrangements described herein, while still providing a high DR digital microphone systems. Further non-limiting embodiments can comprise an exemplary glitch removal component configured to minimize audible artifacts associated with the change in the gain of the exemplary adaptive ADCs.

A differential output current digital-to-analog converter (IDAC) circuit may include a delta-sigma modulator configured to receive a digital input signal, a control circuit responsive to the delta-sigma modulator configured to perform a DAC decode operation, a plurality of DAC elements responsive to the DAC decode operation, the plurality of DAC elements configured to, in concert, generate a differential output current signal based on the digital input signal to a load coupled to a pair of output terminals of the IDAC, and an output impedance coupled between the pair of output terminals such that the output impedance is in parallel with the load.

A fluctuation suppression circuit suppresses fluctuation of a reference voltage supplied to a switched capacitor circuit having a differential configuration. The switched capacitor circuit includes an input capacitor for charging an input voltage and a reference capacitor for charging the reference voltage. The input capacitor and the reference capacitor are separately disposed. The fluctuation suppression circuit includes an electric charge supply circuit. The electric charge supply circuit generates an offset electric charge by adopting a predetermined offset voltage, for offsetting a charged or discharged electric charge generated in the switched capacitor circuit, and supplies the offset electric charge to two reference input nodes, which are supplied with the reference voltage, in the switched capacitor circuit.

A differential output current digital-to-analog (IDAC) circuit may include a delta-sigma modulator configured to receive a digital input signal, a control circuit responsive to the delta-sigma modulator configured to perform a DAC decode operation, a plurality of DAC elements responsive to the DAC decode operation, the plurality of DAC elements configured to, in concert, generate a differential output current signal based on the digital input signal to a load coupled to a pair of output terminals of the IDAC, and a plurality of warming switches, each warming switch coupled to a respective bias transistor of a respective DAC element of the plurality of DAC elements, wherein the control circuit may further be configured to selectively control each such warming switch in order to selectively de-bias and bias a respective bias transistor of such warming switch when a respective DAC element of the respective bias transistor is output-disabled from generating the differential output current signal.

A differential output current digital-to-analog (IDAC) circuit may include a delta-sigma modulator configured to receive a digital input signal, a control circuit responsive to the delta-sigma modulator configured to perform a DAC decode operation, a plurality of DAC elements responsive to the DAC decode operation, the plurality of DAC elements configured to, in concert, generate a differential output current signal based on the digital input signal to a load coupled to a pair of output terminals of the IDAC, and a plurality of warming switches, each warming switch coupled to a respective bias transistor of a respective DAC element of the plurality of DAC elements, wherein the control circuit may further be configured to selectively control each such warming switch in order to selectively de-bias and bias a respective bias transistor of such warming switch when a respective DAC element of the respective bias transistor is output-disabled from generating the differential output current signal.