A differential output current digital-to-analog (IDAC) circuit may include a delta-sigma modulator configured to receive a digital input signal, a control circuit responsive to the delta-sigma modulator configured to perform a DAC decode operation, a plurality of DAC elements responsive to the DAC decode operation, the plurality of DAC elements configured to, in concert, generate a differential output current signal based on the digital input signal to a load coupled to a pair of output terminals of the IDAC, and an output impedance coupled between the pair of output terminals such that the output impedance is in parallel with the load.

A system may include a current digital-to-analog converter (IDAC) configured to convert a digital input signal into an output current signal and a switched-mode power supply configured to provide electrical energy in the form of a supply voltage to the IDAC for operation of the IDAC, the switched-mode power supply configured to track a voltage signal derived from the digital input current signal and generate the supply voltage based on the voltage signal and a voltage headroom above the voltage signal.

A system may include a current digital-to-analog converter (IDAC) configured to convert a digital input signal into an output current signal and a switched-mode power supply configured to provide electrical energy in the form of a supply voltage to the IDAC for operation of the IDAC, the switched-mode power supply configured to track a voltage signal derived from the digital input current signal and generate the supply voltage based on the voltage signal and a voltage headroom above the voltage signal.

A fractional-N phase-locked loop (PLL) has a time-to-voltage converter with second order non linearity. The time-to voltage-converter provides an analog error signal indicating a phase difference between the reference clock signal with a period error and a feedback signal supplied by a fractional-N feedback divider. The spur results in quantization noise associated with the fractional-N feedback divider being frequency translated. To address the frequency translated noise, a spur cancellation circuit receives a residue signal indicative of the quantization noise and a spur signal indicative of the spur. The non-linearity of the time-to-voltage converter is mimicked digitally through terms of a polynomial generated to cancel the noise. The generated polynomial is coupled to a delta sigma modulator that controls a digital to analog converter that adds/subtracts a voltage value to/from the error signal to thereby cancel the quantization noise including the frequency translated quantization noise.

Exemplary multipath digital microphone described herein can comprise exemplary embodiments of adaptive ADC range multipath digital microphones, which allow low power to be achieved for amplifiers or gain stages, as well as for exemplary adaptive ADCs in exemplary multipath digital microphone arrangements described herein, while still providing a high DR digital microphone systems. Further non-limiting embodiments can comprise an exemplary glitch removal component configured to minimize audible artifacts associated with the change in the gain of the exemplary adaptive ADCs.

A pulse density modulation method includes the following steps: S01, obtaining a number of bits n of a binary density value d, setting a number of bits of a counter as n, an initial value of the counter is 0 or 1; S02, searching for a rightmost 1: obtaining a number of bits j of the rightmost 1 of a current value i of the counter counted from right to left; a number in the counter is a binary number; a minimum value of j is 1; S03, determining whether corresponding bits are equal; S04, adding the value i of the counter by 1, proceeding to a next period, and turning to the step S02.

A pulse density modulation method includes the following steps: S01, obtaining a number of bits n of a binary density value d, setting a number of bits of a counter as n, an initial value of the counter is 0 or 1; S02, searching for a rightmost 1: obtaining a number of bits j of the rightmost 1 of a current value i of the counter counted from right to left; a number in the counter is a binary number; a minimum value of j is 1; S03, determining whether corresponding bits are equal; S04, adding the value i of the counter by 1, proceeding to a next period, and turning to the step S02.

Exemplary multipath digital microphone described herein can comprise exemplary embodiments of adaptive ADC range multipath digital microphones, which allow low power to be achieved for amplifiers or gain stages, as well as for exemplary adaptive ADCs in exemplary multipath digital microphone arrangements described herein, while still providing a high DR digital microphone systems. Further non-limiting embodiments can comprise an exemplary glitch removal component configured to minimize audible artifacts associated with the change in the gain of the exemplary adaptive ADCs.

An electric control device includes a first delta sigma modulator having a clock input connection, a second delta sigma modulator having a clock input connection, and an evaluation unit. The evaluation unit includes a first clock output connection which is connected to the clock input connection of the first delta sigma modulator by a first electrical cable, and a second clock output connection which is connected to the clock input connection of the second delta sigma modulator by a second electrical cable. The evaluation unit is designed to generate a clock signal (CLK1) at the first clock output connection (7) in phase opposition to a clock signal (CLK2) at the second clock output connection (9).

An electric control device includes a first delta sigma modulator having a clock input connection, a second delta sigma modulator having a clock input connection, and an evaluation unit. The evaluation unit includes a first clock output connection which is connected to the clock input connection of the first delta sigma modulator by a first electrical cable, and a second clock output connection which is connected to the clock input connection of the second delta sigma modulator by a second electrical cable. The evaluation unit is designed to generate a clock signal (CLK1) at the first clock output connection (7) in phase opposition to a clock signal (CLK2) at the second clock output connection (9).