The present invention provides a fractional-N frequency synthesizer comprising a divider controller comprising a multistage noise Shaping (MASH) digital delta-sigma modulator comprising L stages, wherein the Lth stage is configured to receive as an input a high amplitude dither signal.

An electronic circuit for a microphone and a microphone are disclosed. In an embodiment, the electronic circuit includes a sigma-delta modulator having a configurable resolution and a mode selector, wherein the sigma-delta modulator is selectively operable in at least two operation modes and the mode selector is configured to determine a desired operation mode dependent on an externally provided control signal and to select the resolution of the sigma-delta modulator according to the determined operation mode.

A delta-sigma modulator may comprise a loop filter for integrating and outputting a difference between an input signal and an analog signal; a quantizer for quantizing and outputting a signal output from the loop filter; and a digital-to-analog converter (DAC) for outputting the analog signal by digital-to-analog converting a signal output from the quantizer. Also, the loop filter may comprise an operational amplifier; and a circuit including at least one capacitor, at least one resistor, and at least one switch which are connected to the operational amplifier. Also, signal transfer characteristics of the loop filter satisfy a third-order transfer function or a second-order transfer function by turning on or off the at least one switch.

A delta-sigma modulator may comprise a loop filter for integrating and outputting a difference between an input signal and an analog signal; a quantizer for quantizing and outputting a signal output from the loop filter; and a digital-to-analog converter (DAC) for outputting the analog signal by digital-to-analog converting a signal output from the quantizer. Also, the loop filter may comprise an operational amplifier; and a circuit including at least one capacitor, at least one resistor, and at least one switch which are connected to the operational amplifier. Also, signal transfer characteristics of the loop filter satisfy a third-order transfer function or a second-order transfer function by turning on or off the at least one switch.

A CMOS image sensor including a plurality of pixels, each including: a photodiode; a sigma-delta modulator of order p, p being an integer greater than or equal to 1, capable of delivering a binary digital signal representative of the illumination level of the photodiode; and a configurable connection circuit enabling to couple the sigma-delta modulator of the pixel to a sigma-delta modulator of another pixel, so that the modulators of the two pixels form with each other a sigma-delta modulator of order greater than p.

There is provided an adversarial self-supervised learning method for a sigma delta modulation device. The device comprises a loop filter including an operational amplifier, and a circuit including a plurality of capacitors, a plurality of resistors, and a plurality of switches, which are connected to the operational amplifier; a quantization part quantizing and outputting a signal that is output from the loop filter; a feed-back converter converting a digital signal output from the quantization part into an analog signal; a memory configured to store one or more instructions; and a processor configured to control turn on or off of the plurality of switches, and adjust resistor values in an equivalent circuit of the loop filter in order to compensate a notch frequency reduced in the loop filter for satisfying a second-order transfer function.

In described examples, an integrated circuit (IC) includes first and second integrators, first and second weighted summers, first and second digital-to-analog converters (DACs), and a quantizer. First and second inputs of the first weighted summer are respectively connected to an output of the first integrator and an output of the second DAC. An input of the second integrator is connected to an output of the first weighted summer. An input of the second weighted summer is connected to an output of the second integrator. An input of the quantizer is connected to an output of the second weighted summer. Inputs of the first and second DACs are connected to respective outputs of the quantizer. An output of the first DAC is connected to a first input of the first integrator. A second input of the first integrator and a third input of the first weighted summer are analog signal inputs.