Provided is a delta-sigma modulator including a first integral unit configured to integrate an input analog signal, a second integral unit configured to integrate a signal output by the first integral unit, a quantizer configured to quantize a signal output by the second integral unit, a DA converter configured to perform DA conversion on an output of the quantizer and output a feedback signal to be fed back to the first integral unit, and a control unit configured to perform control to cause the first integral unit and the second integral unit to perform different integral operations during a first period and a second period, in which the second integral unit is configured to receive the feedback signal output by the DA converter via the first integral unit and integrate the feedback signal during the first period and the second period.

An image sensor includes a pixel array, a controller, and a plurality of analog-to-digital converters. The pixel array includes a plurality of pixels coupled to column lines, respectively, and the plurality of pixels are configured to sense incident lights to generate analog signals through the column lines. The controller generate a conversion control signal that is configurable based on changes of at least one operational condition. The plurality of analog-to-digital converters are coupled to the column lines, respectively. The plurality of analog-to-digital converters perform a delta-sigma modulation and a digital filtering to convert the analog signals to digital signals. The plurality of analog-to-digital converters adjust a conversion gain internally in response to the conversion control signal.

A DAC error measurement apparatus includes: an ADC and a feedback DAC, where a measurement input of the ADC includes a square wave signal with a constant frequency, a direct-current signal at a constant logical level, and an analog output of the feedback DAC; a measurement selection module, configured to provide a measured digit in a digital output to a separately selected source cell, and provide remaining digits in the digital output to remaining source cells, where the measured digit is a flippable digit, and the remaining digits are non-flipping digits; and a measurement module, configured to measure an amplitude of the digital output based on the digital output. One flipping digit in the digital output is the measured digit, and the remaining digits are the non-flipping digits, such that the measurement selection module may separately select one source cell to receive the measured digit.

An analog-to-digital converter (ADC) is provided. The ADC receives an analog input signal and generates a digital code. The ADC includes a sigma-delta modulator (SDM), a decimation filter and a detection circuit. The SDM includes a loop filter, a quantizer and a digital-to-analog converter (DAC). The loop filter receives the analog input signal. The quantizer is coupled to the loop filter and quantizes an output of the loop filter to generate a digital output signal. The DAC is coupled to the quantizer and the loop filter. The decimation filter is coupled to the SDM and converts the digital output signal into the digital code. The detection circuit is coupled to the SDM and detects a node voltage of the SDM and generate a control signal. The control signal is utilized to control the loop filter, the quantizer, a feedback path of the SDM and/or a feedforward path of the SDM.

Disclosed is an image sensor including pixels, and an analog digital converter configured to select output values of the pixels using an analog multiplexer and to simultaneously perform a convolution operation and conversion into a digital signal using a delta-sigma ADC. The size of processed data is reduced, and power consumption is reduced, and thus the image sensor is advantageously applied to a portable device.

An analog-to-digital converter (ADC) is provided. The ADC receives an analog input signal and generates a digital code. The ADC includes a sigma-delta modulator (SDM), a decimation filter and a detection circuit. The SDM includes a loop filter, a quantizer and a digital-to-analog converter (DAC). The loop filter receives the analog input signal. The quantizer is coupled to the loop filter and quantizes an output of the loop filter to generate a digital output signal. The DAC is coupled to the quantizer and the loop filter. The decimation filter is coupled to the SDM and converts the digital output signal into the digital code. The detection circuit is coupled to the SDM and detects a node voltage of the SDM and generate a control signal. The control signal is utilized to control the loop filter, the quantizer, a feedback path of the SDM and/or a feedforward path of the SDM.

A DAC error measurement apparatus includes: an ADC and a feedback DAC, where a measurement input of the ADC includes a square wave signal with a constant frequency, a direct-current signal at a constant logical level, and an analog output of the feedback DAC; a measurement selection module, configured to provide a measured digit in a digital output to a separately selected source cell, and provide remaining digits in the digital output to remaining source cells, where the measured digit is a flippable digit, and the remaining digits are non-flipping digits; and a measurement module, configured to measure an amplitude of the digital output based on the digital output. One flipping digit in the digital output is the measured digit, and the remaining digits are the non-flipping digits, such that the measurement selection module may separately select one source cell to receive the measured digit.

The present invention provides a fractional-N frequency synthesizer comprising a divider controller comprising a multistage noise Shaping (MASH) digital delta-sigma modulator comprising L stages, wherein the Lth stage is configured to receive as an input a high amplitude dither signal.

An electronic circuit for a microphone and a microphone are disclosed. In an embodiment, the electronic circuit includes a sigma-delta modulator having a configurable resolution and a mode selector, wherein the sigma-delta modulator is selectively operable in at least two operation modes and the mode selector is configured to determine a desired operation mode dependent on an externally provided control signal and to select the resolution of the sigma-delta modulator according to the determined operation mode.

A continuous-time analog-to-digital converter (ADC) includes a plurality of integrators selectively coupled in series. The ADC may further include a quantizer with excess loop delay (ELD) compensation. The quantizer may be coupled in series to a least one integrator. The ELD compensation may be programmable based on a transfer function of the ADC. The ADC may further include parallel digital-to-analog converters (DACs). Each DAC may have an input coupled to an output of the quantizer, and an output coupled to an input of a corresponding integrator. The ADC may further include a bypass path coupled to an input or output of one of the integrators. The bypass path may be configured to selectively bypass one or more of the integrators to change the transfer function of the ADC.