A high-speed digital transmitter for wireless communication systems includes a plurality of transmitter chain circuits configured to respectively receive incoming component signals having a first frequency and to produce outgoing transmission signals having a second frequency greater than the first frequency in a first domain. In some aspects, the incoming component signals are up-sampled to the second frequency using a plurality of streams processed concurrently at a predetermined sample rate over a predetermined number of interpolation filter stages in each of the plurality of transmitter chain circuits. The high-speed digital transmitter also includes a serializer configured to combine the outgoing transmission signals from the plurality of transmitter chain circuits into a serialized transmission signal having a third frequency greater than the second frequency in a second domain different from the first domain.

An audio activity detector device is disclosed. The audio activity detector device comprises a closed loop feedback regulating circuit that supplies an input signal representative of a time-varying voltage signal to a quantizer circuit, wherein the quantizer circuit, as a function of the input signal, converts the input signal to a quantizer discrete-time signal; a first circuit that, as a function of the discrete-time signal, determines a key quantizer statistic value for the quantizer discrete-time signal; and a second circuit that, as a function of the key quantizer statistic value, determines a signal statistic value for the input signal and a gain control value.

To effectively suppress an idle tone in a delta-sigma modulator that generates a feedback signal by a digital-to-analog converter. A filter integrates a difference between an input analog signal and a feedback signal, and outputs the integrated difference as an integrated signal. A preceding-stage quantizer quantizes an integrated signal into a digital signal, and outputs the resulting digital signal as a preceding-stage output signal. An adder adds a predetermined dithering signal to a preceding-stage output signal, and outputs the resulting signal as a subsequent-stage input signal. A subsequent-stage quantizer configured to quantize the subsequent-stage input signal into a digital signal of a shorter number of bits than a preceding-stage output signal, and outputs the resulting digital signal as a subsequent-stage output signal. A digital-to-analog converter configured to convert a subsequent-stage output signal into an analog signal, and outputs the resulting analog signal to a filter as a feedback signal.

The present application provides a noise shaping circuit including a first modulation unit, configured to generate a first digital output signal according to a first digital input signal, the first modulation unit comprising a first quantizer; a first subtractor, coupled to an input terminal and an output terminal of the first quantizer, configured to generate a first quantization noise; and a second modulation unit, configured to generated a second digital output signal according to a second digital input signal, wherein the second digital input signal is related to the first quantization noise; wherein the noise shaping circuit generates an overall analog output signal according to the first digital output signal and the second digital output signal.

In accordance with embodiments of the present disclosure, a processing system may include a plurality of processing paths including a first processing path and a second processing path, a digital-to-analog stage output, and a controller. The first processing path may include a first digital-to-analog converter for converting the digital input signal into a first intermediate analog signal, the first digital-to-analog converter configured to operate in a high-power state and a low-power state. The second processing path may include a second digital-to-analog converter for converting a digital input signal into a second intermediate analog signal. The digital-to-analog stage output may be configured to generate an analog signal comprising a sum of the first intermediate analog signal and the second intermediate analog signal. The controller may be configured to operate the first digital-to-analog converter in the lower-power state when a magnitude of the digital input signal is below a threshold magnitude.