An exemplary incremental two-step capacitance-to-digital converter (CDC) with a time-domain sigma-delta modulator (TDΔΣM) includes a voltage-controlled oscillator (VCO)-based integrator that can be used in a low-order loop configuration. Example prototypes are disclosed, which when fabricated in 40-nm CMOS technology, provides CDC resolution of 0.29 fF while dissipating only 0.083 nJ per conversion.

A method of applying digital pre-distortion includes: outputting, by a look-up table, a first table value based on an input digital signal; adding the first table value and the input digital signal to generate a first combined signal comprising a first combined value having a first integer coefficient and a first fractional coefficient; separating the first integer coefficient from the first fractional coefficient to generate a first integer signal representing the first integer coefficient and a first fractional signal representing the first fractional coefficient; generating a delta-sigma modulated signal based on the first fractional signal; converting, by a first digital-to-analog, a first digital signal into a first analog signal, wherein the first digital signal is representative of the first integer signal; and converting, by a second DAC, a second digital signal into a second analog signal, wherein the second digital signal is representative of the delta-sigma modulated signal.

The present invention provides a fractional-N frequency synthesizer comprising a divider controller comprising a multistage noise Shaping (MASH) digital delta-sigma modulator comprising L error feedback modulator (EFM) stages, wherein the jth EFM stage is configured to receive as an input the sum of the error of the preceding EFM stage and a high amplitude dither signal derived from the error of the kth EFM stage, where 1≤j≤k≤L.

A passive sigma-delta modulator including first modulator loop, a second modulator loop, and a digital combiner providing an output signal. The first modulator loop includes a first quantizer, a first passive summing junction, a first continuous-time passive analog loop filter, and a first feedback path. The second modulator loop includes a second quantizer, analog transfer circuitry, a second continuous-time passive summing junction, a second passive analog loop filter, a second feedback path, and digital transfer circuitry having a gain that is substantially a reciprocal of the analog transfer circuitry. A digital noise cancelation filter may be located between the first quantizer and the digital combiner, or an analog noise cancelation filter may be provided within the second modulator loop. Single-ended or differential configurations are contemplated.

Provided is an AD converter, including: an analog signal input circuit, configured to be input with an analog input signal, and output a first analog output signal based on the analog input signal and a second analog output signal based on the analog input signal at different timing; an integral circuit, configured to integrate the first analog output signal and the second analog output signal and output the first integral signal and the second integral signal; a predictive circuit, configured to predict an integral signal output after the output by the integral circuit based on the first integral signal and the second integral signal output by the integral circuit, and output a predictive integral signal; and a quantization circuit, configured to generate a digital signal with the predictive integral signal quantized.

A series-connected delta-sigma modulator (DSM) comprises a first DSM, configured to receive an input signal, comprising a first loop filter, configured to generate a first processed signal; and a first quantizer, coupled to the first loop filter, configured to generate a first quantized signal, and to feed back the first quantized signal to the first loop filter, wherein the first quantized signal comprises a clipping error smaller than a first predetermined value; and a second DSM, coupled to the first DSM, configured to receive the first quantized signal from the first DSM, comprising a second loop filter, configured to generate a second processed signal; and a second quantizer, coupled to the second loop filter, configured to generate a second quantized signal, and to feed back the second quantized signal to the second loop filter, wherein the second quantized signal comprises a quantization error smaller than a second predetermined value.

An ANC system includes an AD converter which performs AD conversion on an external noise signal, an ANC signal generator which generates an ANC signal for canceling a noise component arriving at the ears of a user based on an output signal of the AD converter, and a level detector which detects a level of the output signal and causes the ANC signal generator to power down in response to the level. The level detector measures a time for which the level is equal to or less than a predetermined first threshold value, causes the ANC signal generator or a portion of blocks of the AD converter to power down after the measured time exceeds a predetermined value, and causes the ANC signal generator or a portion of blocks of the AD converter to return from the power down when the level exceeds a predetermined second threshold value.

A current to digital converter circuit has an integrator amplifier with an input adapted to receive a current signal and an output adapted to provide a voltage signal as a function of an integration of the current signal, a quantizer circuit with an input which is coupled to the output of the integrator amplifier and with an output adapted to provide a binary result signal as a function of a comparison of the voltage signal with at least a first reference voltage signal, a digital-to-analog converter circuit which is coupled in a switchable manner as a function of the binary result signal to the input of the integrator amplifier, and a controlled current source which is coupled to the output of the integrator amplifier via a first switch which is controlled as a function of the binary result signal such that an auxiliary current is supplied to the output of the integrator amplifier.

A noise-shaping enhanced (NSE) gated ring oscillator (GRO)-based ADC includes a delay which delays and feedbacks an error signal to an input of the NSE GRO-based ADC. The feedback error signal provides an order of noise-shaping and the error signal is generated at the input of the NSE GRO-based ADC from an input signal, the feedback error signal, and a front-end output. A voltage-to-time converter converts the error signal to the time domain. A GRO outputs phase signals from the time domain error signal by oscillating when the error signal is high and inhibiting oscillation otherwise. A quantization device quantizes the phase signals to generate the front-end output. A quantization extraction device determines a quantization error from the quantized phase signals. A time-to-digital converter digitizes the quantization error to generate a back-end output. An output device generates a second order noise-shaped output based on the front-end and the back-end outputs.

A method of applying digital pre-distortion includes: outputting, by a look-up table, a first table value based on an input digital signal; adding the first table value and the input digital signal to generate a first combined signal comprising a first combined value having a first integer coefficient and a first fractional coefficient; separating the first integer coefficient from the first fractional coefficient to generate a first integer signal representing the first integer coefficient and a first fractional signal representing the first fractional coefficient; generating a delta-sigma modulated signal based on the first fractional signal; converting, by a first digital-to-analog, a first digital signal into a first analog signal, wherein the first digital signal is representative of the first integer signal; and converting, by a second DAC, a second digital signal into a second analog signal, wherein the second digital signal is representative of the delta-sigma modulated signal.