A delta-sigma modulator may include a loop filter, a quantizer, an input gain element having a programmable input gain and coupled between an input of the delta-sigma modulator and an input of the loop filter, a feedforward gain element having a programmable feedforward gain and coupled between the input of the delta-sigma modulator and an output of the loop filter, and a quantizer gain element having a quantizer gain and coupled between the output of the loop filter and an input of the quantizer. The programmable input gain is controlled in order to control a variable gain of the delta-sigma modulator. The programmable feedforward gain is controlled to be equal to the ratio of the programmable input gain and the quantizer gain such that the delta-sigma modulator has a fixed phase response.

An impedance sensing circuit includes first and second current sources and first and second bias current sources that are appropriately coupled to first and second resistors. The impedance sensing circuit also includes a comparator that compares a first voltage based on the first terminal of the first resistor to a second voltage based on the first terminal of the second resistor to generate a comparator output signal. Either the comparator output signal or a digital signal based on the comparator output signal operates to regulate the current signals output from the first and second current sources so that the first voltage is same as the second voltage. The comparator output signal and the digital signal is representative of a difference between the first voltage and the second voltage that is based on an impedance difference between the first resistor and the second resistor.

A high resolution analog to digital converter (ADC) with improved bandwidth senses an analog signal (e.g., a load current) to generate a digital signal. The ADC operates based on a load voltage produced based on charging of an element (e.g., a capacitor) by a load current and a digital to analog converter (DAC) output current (e.g., from a N-bit DAC). The ADC generates a digital output signal representative of a difference between the load voltage and a reference voltage. This digital output signal is used directly, or after digital signal processing, to operate an N-bit DAC to generate a DAC output current that tracks the load current. In addition, quantization noise is subtracted from the digital output signal thereby extending the operational bandwidth of the ADC. In certain examples, the operational bandwidth of the ADC extends up to 100s of kHz (e.g., 200-300 kHz), or even higher.

A semiconductor device such as a sigma delta A/D converter comprises an integrator configured to output first and second output signals, a quantizer configured to generate a first digital signal based on the output signals, first and second switches configured to control application of first and second reference voltages to a first resistor based on respective first and second control signals, and a third switch configured to control connection between the first resistor and a first input terminal of the integrator based on a third control signal. The first through third control signals are generated based on the first digital signal and a second digital signal obtained by delaying the first digital signal. The third switch is turned on when any one of the first and second switches is turned on, and is turned off when both the first and second switches are turned off.

An analog to digital converter (ADC) that is configured to service a photo-diode includes a capacitor and a self-referenced latched comparator. The capacitor produces a photo-diode voltage based on charging by a photo-diode current associated with the photo-diode and a digital to analog converter (DAC) source current and/or a DAC sink current. The self-referenced latched comparator generates a first digital signal that is based on a difference between the photo-diode voltage and a threshold voltage associated with the self-referenced latched comparator. Also, one or more processing modules executes operational instructions to process the first digital signal to generate a second digital signal and/or a third digital signal. An N-bit DAC generates the DAC source current based on the second digital signal, and an M-bit DAC generates the DAC sink current based on the third digital signal. The DAC source current and/or the DAC sink current tracks the photo-diode current.

The present invention relates to a sigma-delta analogue-to-digital converter. The sigma-delta analogue-to-digital converter comprises a transconductance stage having first, second and third terminals. A capacitor is connected in parallel at the third terminal. Further, the sigma-delta analogue-to-digital converter comprises a quantiser at the third terminal of the transconductance stage with feedback by a voltage digital-to-analogue converter for feeding back a feedback signal to one of the terminals of the transconductance stage.

An analog to digital converter (ADC) that is configured to service a photo-diode includes a capacitor and a self-referenced latched comparator. The capacitor produces a photo-diode voltage based on charging by a photo-diode current associated with the photo-diode and a digital to analog converter (DAC) source current and/or a DAC sink current. The self-referenced latched comparator generates a first digital signal that is based on a difference between the photo-diode voltage and a threshold voltage associated with the self-referenced latched comparator. Also, one or more processing modules executes operational instructions to process the first digital signal to generate a second digital signal and/or a third digital signal. An N-bit DAC generates the DAC source current based on the second digital signal, and an M-bit DAC generates the DAC sink current based on the third digital signal. The DAC source current and/or the DAC sink current tracks the photo-diode current.

A delta-sigma modulator includes a quantizer, a signal propagation path including a plurality of cascaded integrators coupled between the input node and the quantizer, and a feedback network including a plurality of digital-to-analog converters. In a calibration mode of operation, a first digital-to-analog converter of the plurality of digital-to-analog converters of the feedback network receives a signal including a periodic alternated digital sequence, the first digital-to-analog converter being coupled to a first integrator of the plurality of cascaded integrators, integrators of the plurality of cascaded integrators other than the first integrator operate in a gain mode of operation, the delta-sigma modulator generates a digital test signal at an output of the quantizer based on the signal including the periodic alternated digital sequence, and calibration circuitry generates a calibration signal based on the digital test signal and a reference digital word.

A high resolution analog to digital converter (ADC) with improved bandwidth senses an analog signal (e.g., a load current) to generate a digital signal. The ADC operates based on a load voltage produced based on charging of an element (e.g., a capacitor) by a load current and a digital to analog converter (DAC) output current (e.g., from a N-bit DAC). The ADC generates a digital output signal representative of a difference between the load voltage and a reference voltage. This digital output signal is used directly, or after digital signal processing, to operate an N-bit DAC to generate a DAC output current that tracks the load current. In addition, quantization noise is subtracted from the digital output signal thereby extending the operational bandwidth of the ADC. In certain examples, the operational bandwidth of the ADC extends up to 100s of kHz (e.g., 200-300 kHz), or even higher.

A high resolution analog to digital converter (ADC) with improved bandwidth senses an analog signal (e.g., a load current) to generate a digital signal. The ADC operates based on a load voltage produced based on charging of an element (e.g., a capacitor) by a load current and a digital to analog converter (DAC) output current (e.g., from a N-bit DAC). The ADC generates a digital output signal representative of a difference between the load voltage and a reference voltage. This digital output signal is used directly, or after digital signal processing, to operate an N-bit DAC to generate a DAC output current that tracks the load current. In addition, quantization noise is subtracted from the digital output signal thereby extending the operational bandwidth of the ADC. In certain examples, the operational bandwidth of the ADC extends up to 100s of kHz (e.g., 200-300 kHz), or even higher.