Described herein is an apparatus and method for enhancing the dynamic range of an analog-to-digital converter (ADC). In one embodiment of the present approach, an analog input signal is amplified in a programmable gain amplifier (PGA) before the ADC receives the signal, so that the gain applied to an input signal, and gain (or attenuation) later applied in order to balance the overall gain of the circuit, occurs only in either the analog domain; in the prior art, gain occurs partly in each domain. The ADC gain is then adjusted to compensate for gain of the PGA and balance the overall gain of the circuit. In another embodiment, the ADC gain is adjusted, and gain of a digital gain element that receives the signal from the ADC is adjusted to compensate for the ADC gain and balance the overall gain of the circuit, eliminating the need for a PGA.

An image sensor includes a pixel array, a controller, and a plurality of analog-to-digital converters. The pixel array includes a plurality of pixels coupled to column lines, respectively, and the plurality of pixels are configured to sense incident lights to generate analog signals through the column lines. The controller generate a conversion control signal that is configurable based on changes of at least one operational condition. The plurality of analog-to-digital converters are coupled to the column lines, respectively. The plurality of analog-to-digital converters perform a delta-sigma modulation and a digital filtering to convert the analog signals to digital signals. The plurality of analog-to-digital converters adjust a conversion gain internally in response to the conversion control signal.

A system including a circuit, including a first preamplifier, a sampling switch, a regenerative latch, and a second preamplifier aligned in a pipelined sequence with the first preamplifier, wherein the first and second preamplifier are associated with dynamic comparator and configured to gain signal utilizing multiple cascaded gains and sample-and-hold stages including a plurality of phases.

A circuit includes a programmable gain amplifier (PGA) having a PGA output. The circuit further includes a delta-sigma modulator having an input coupled to the PGA output. The circuit also includes a digital filter and a dynamic range enhancer (DRE) circuit. The digital filter is coupled to the delta-sigma modulator output. The DRE circuit is coupled to the delta-sigma modulator output and to the PGA. The DRE circuit is configured to monitor a signal level of the delta-sigma modulator output. Responsive to the signal level being less than a DRE threshold, the DRE circuit is configured to program the PGA for a gain level greater than unity gain and to cause the digital filter to implement an attenuation of a same magnitude as the gain level to be programmed into the PGA.

A Sigma-Delta analog to digital converter (ADC) is described. The Sigma-Delta ADC includes a series arrangement of a gain tracker, a first discrete-time integrator stage and a quantizer between an ADC input and an ADC output. The Sigma-Delta ADC includes a digital to analog converter (DAC) having a DAC input and a DAC output connected to the gain tracker. The Sigma-Delta analog to digital converter includes a controller having a control input connected to the quantizer output. The controller provides a digital input to the DAC input and provides a gain control signal to the gain tracker.

A circuit includes a programmable gain amplifier (PGA) having a PGA output. The circuit further includes a delta-sigma modulator having an input coupled to the PGA output. The circuit also includes a digital filter and a dynamic range enhancer (DRE) circuit. The digital filter is coupled to the delta-sigma modulator output. The DRE circuit is coupled to the delta-sigma modulator output and to the PGA. The DRE circuit is configured to monitor a signal level of the delta-sigma modulator output. Responsive to the signal level being less than a DRE threshold, the DRE circuit is configured to program the PGA for a gain level greater than unity gain and to cause the digital filter to implement an attenuation of a same magnitude as the gain level to be programmed into the PGA.

A Sigma-Delta analog to digital converter (ADC) is described. The Sigma-Delta ADC includes a series arrangement of a gain tracker, a first discrete-time integrator stage and a quantizer between an ADC input and an ADC output. The Sigma-Delta ADC includes a digital to analog converter (DAC) having a DAC input and a DAC output connected to the gain tracker. The Sigma-Delta analog to digital converter includes a controller having a control input connected to the quantizer output. The controller provides a digital input to the DAC input and provides a gain control signal to the gain tracker.

A system, comprising: a sigma-delta modulator using an integrator of a cascade-of-integrator feedback topology to perform operations is disclosed. The operations can comprise in response to receiving a gain value, applying the gain value to a group of feed-forward coefficients, determining a change in the gain value, and adjusting, during a clock cycle of a defined time period, a plurality of state variables of the sigma-delta modulator by multiplying each of the state variables by the scale factor that is a ratio of the gain value after determining the change in the gain value the gain value before determining the change in the gain value.

A continuous-time sigma delta modulator circuit includes a scaling circuit that scales an input analog signal by a selectable range of different scaling factors in order to change a range of signal levels of the input analog signal to a desired range of signal levels in a scaled analog signal prior to conversion of the scaled analog signal to a digital signal. The scaling factor is selected based on the range of signal levels of the input analog signal in order to provide signal levels of the scaled signal within a desired range. The scaling circuit maintains current flow of the input analog signal at a substantially constant level regardless of the different scaling factors that are used to scale the input analog signal.

A current mode sigma-delta modulator comprises an input node; a comparator that compares a voltage of the input node to a reference voltage and outputs a comparison result; an integrating capacitor connected to an input of the comparator; and a switched capacitor circuit connected at a first end to the input node, the input of the comparator, and the integrating capacitor, and connected at a second end to an output of the comparator. The current mode sigma-delta modulator is a component of an analog-to-digital converter.