A device includes a sensor configured to output an analog sensor signal, an analog-to-digital converter circuit configured to convert the analog sensor signal into a sigma-delta-modulated digital signal having a bit width of n bits, and a pulse width modulator configured to generate a pulse-width-modulated signal based on the sigma-delta-modulated digital signal.

A DAC circuit includes: a PWM encoding circuit for converting a digital signal to first and second PWM signals, whereby a combination of the first and second PWM signals becomes a PWM encoded signal of at least 3 levels including a positive, a zero and a negative level, wherein the digital signal represents a number in a numerical range; and a demodulation circuit for generating the analog signal according to the first and second PWM signals. The first and second PWM signals have a minimum duty larger than 0 when the digital signal represents a middle number in the numerical range. The zero level of the combination of the first and second PWM signals has a duty which decreases as a difference between the number represented by the digital signal and the middle number increases.

A signal modulation device comprising: an input for receiving a complex input signal (106) comprising an in-phase component signal and a quadrature-phase component signal, a sigma-delta modulator (110) for modulating the complex input signal at an oversampling clock rate (F1) into an intermediary signal (112), a numerical oscillator (60) for generating a phase signal (61) oscillating at a selected carrier frequency (FC), wherein the phase signal takes a finite number of quantized states, and a symbol mapping table (114) comprising a predefined quantized symbol for each quantized complex state of the intermediary signal and each quantized state of the phase signal, and operates at each oversampling clock period (F1) to select a quantized symbol (116) as a function of a current quantized complex state of the intermediary signal (112) and a current quantized state of the phase signal (61).

An audio amplifier system is described comprising: a variable gain audio processor for processing digital audio signal, a digital to analog converter coupled to the audio processor, and configured to receive the processed digital audio signal, a variable gain amplifier having an input coupled to the output of the digital to analog converter and operably connected to a power supply, a controller coupled to the variable gain audio processor and the variable gain amplifier and configured to switch the audio amplifier system between a first operating mode having a first power supply voltage value and a second operating mode having a second higher power supply voltage value; wherein the controller is operable in the first operating mode to set the audio amplifier system gain to a desired gain value and in the second operating mode to maintain the desired gain value.

A method, applied in a driving circuit including a bidirectional circuit coupled between a voltage source and a load, includes receiving a feedback signal from the load and an input signal; generating a plurality of pulse width modulation (PWM) signals according to the input signal and the feedback signal; driving the load by the bidirectional circuit according to the plurality of PWM signals such that the input signal and the feedback signal are substantially proportional to each other. The input signal is a time varying signal. The step of generating a PWM signal among the plurality of PWM signals according to the input signal and the feedback signal includes determining a difference according to the input signal and the feedback signal; and generating the PWM signal with a pulse width. The pulse width is determined according to the difference.

A digital-to-analog conversion device which performs integration processing for integrating a difference between an input signal and a first return signal generated based on the input signal, and outputting an integration result, first quantization processing for quantizing the integration result, and outputting a first quantization signal, first return signal output processing for outputting the first return signal by adding to the first quantization signal a correction value delay signal acquired by a correction value signal outputted based on the integration result being delayed, and output processing for outputting output signals including a signal whose pulse width is asymmetrical to center of a processing period, based on the first quantization signal, in which the correction value signal includes a signal indicating a correction value for correcting a difference between a center of the pulse width asymmetrical to the center of the processing period and the center of the processing period.

A digital-to-analog conversion device which performs integration processing for integrating a difference between an input signal and a first return signal generated based on the input signal, and outputting an integration result, first quantization processing for quantizing the integration result, and outputting a first quantization signal, first return signal output processing for outputting the first return signal by adding to the first quantization signal a correction value delay signal acquired by a correction value signal outputted based on the integration result being delayed, and output processing for outputting output signals including a signal whose pulse width is asymmetrical to center of a processing period, based on the first quantization signal, in which the correction value signal includes a signal indicating a correction value for correcting a difference between a center of the pulse width asymmetrical to the center of the processing period and the center of the processing period.

This application describes an amplifier circuit (200) with a forward signal path with a class-D output stage (102) for generating a driving signal (Sout) based on a digital input signal (Sin). The amplifier has a first feedback path for providing a first digital feedback signal (Sfb1) based on the driving signal and a second feedback path for providing a second digital feedback signal (Sfb2) from a digital part of the forward signal path. The digital input signal (Sin) is combined with a selected feedback signal (Sfbs). The amplifier circuit is selectively operable in a first mode, in which the first feedback signal is used as the selected feedback signal, and in a second mode, in which the second feedback signal is used as the selected feedback signal. A calibration module (204) is operable to calibrate the first feedback path to reduce any DC offset when the amplifier circuit is operating in the second mode.

A digital-to-analog conversion device which performs integration processing for integrating a difference between an input signal and a first return signal generated based on the input signal, and outputting an integration result, first quantization processing for quantizing the integration result, and outputting a first quantization signal, first return signal output processing for outputting the first return signal by adding to the first quantization signal a correction value delay signal acquired by a correction value signal outputted based on the integration result being delayed, and output processing for outputting output signals including a signal whose pulse width is asymmetrical to center of a processing period, based on the first quantization signal, in which the correction value signal includes a signal indicating a correction value for correcting a difference between a center of the pulse width asymmetrical to the center of the processing period and the center of the processing period.

Systems and methods are provided for architectures for an analog feedback class D modulator that increase the power efficiency of the class D modulator. In particular, systems and methods are provided for an analog feedback class D modulator having a digital feed-forward loop. The digital feed-forward loop allows for removal of signal content from an input to an analog-to-digital converter, such that the ADC processes just noise and/or error. Using the techniques discussed herein, the loop filter is low power as it processes error content but not signal content.