A method for differentiator-based compression of digital data includes (a) multiplying a tap-weight vector by an original data vector to generate a predicted signal, the original data vector comprising N sequential samples of an original signal, N being an integer greater than or equal to one, (b) using a subtraction module, subtracting the predicted signal from a sample of the original signal to obtain an error signal, (c) using a quantization module, quantizing the error signal to obtain a quantized error signal, and (d) updating the tap-weight vector according to changing statistical properties of the original signal.

The present invention suppresses the data size of a data frame to be transmitted to a control device at every control period even if oversampling is performed. A counter unit (10) compresses the data size of sampling data (Sd) indicating a second or subsequent count value (Ct) to the number of bits by which the maximum (Vmax) of a count value countable in one sampling processing can be represented.

The invention provides a system improving signal handling, e.g., transmission and/or processing. In an embodiment, the system may include a filter circuit, a magnitude bit truncation circuit and a utility circuit. The filter circuit may be coupled to a target signal which contains one or more desired signals at one or more interested bands, for attenuating each said interested band to form a filtered signal. The magnitude bit truncation circuit may be coupled to the filter circuit, for truncating one or more bits of each sample of the filtered signal to form a truncated signal. The utility circuit may be coupled to the magnitude bit truncation circuit, for handling the truncated signal to implement handling of the target signal, so as to reduce resource requirement and enhance error tolerance comparing with directly handling the target signal.

A method for encoding or decoding at least one image, an image being split into blocks of elements. The method includes, for at least one block: splitting the block into at least two areas; and processing at least one of the areas. The processing includes scanning the elements of the area according to a predetermined scanning order, and for at least one scanned element, called a current element: selecting at least one predictor element previously encoded or decoded according to a prediction function; and predicting the current element: from the at least one predictor element, if the at least one predictor element belongs to the area; or from at least one replacement value, otherwise.

An apparatus for mitigating nonlinearity-induced spurs and noise in a fractional-N frequency synthesizer

A digital delta-sigma modulator (DDSM) is disclosed with an input signal x[n], an output signal y[n], a quantization error signal e[n] and a dither signal d[n], having an equation described in the z-domain by

Y(z)=STF(z)X(z)+DTF(z)D(z)−NTF(z)E(z)

wherein Y(z), X(z), D(z) andE(z) are z-transforms of the output signal, the input signal, the dither signal, and the quantization error signal, and wherein STF (z), DTF(z) and NTF(z) correspond to a transfer function of the input signal, a transfer function of the dither signal, and a transfer function of the quantization error signal, and wherein the transfer function of the quantization error signal is of the form:

[00001]$\mathrm{NTF}\left(z\right)={\mathrm{Az}}^{-Q}\left(1-z^{-1}\right)\left(1+\underset{i=1}{\overset{K}{.Math.}}{c}_i{z}^{-i}\right)$

where A , Q and K are constants, coefficients c.sub.i are real valued and c.sub.K≠0 and wherein at least one of the zeroes z.sub.j of

[00002]$\left(1+\underset{i=1}{\overset{K}{.Math.}}{c}_i{z}^{-i}\right)$

satisfies z.sub.j≠+1 for j=1, 2, . . . , K

Systems and methods for a power-efficient 3-level digital-to-analog converter. A converter cell using a current starving technique keeps a portion of the converter cell turned on in a low power mode, as opposed to completely turning off current in selected modes. A conversion system keeps a first set of converters active while allowing a second set of converters to be powered down. Systems and methods presented save power and allow for efficient reactivation of converters.

The present invention suppresses the data size of a data frame to be transmitted to a control device at every control period even if oversampling is performed. A counter unit (10) compresses the data size of sampling data (Sd) indicating a second or subsequent count value (Ct) to the number of bits by which the maximum (Vmax) of a count value countable in one sampling processing can be represented.

Systems and methods for improving noise efficiency in a Delta Sigma modulator. A bypass scheme for a noise splitter is disclosed that reduces toggling activity for small signals. In particular, a sample-by-sample bypass noise splitter is disclosed that includes a noise splitting module and a bypass line. The bypass line bypasses the noise splitting module when signals are below a selected threshold, increasing efficiency of the system.

A receiver includes an interface and a processor. The interface is configured to receive a signal including symbols carrying bit values in respective symbol intervals, and to convert the received signal into a serial sequence of digital samples, the received signal being modulated using a Differential Manchester Encoding (DME) scheme that (i) represents a first bit value by a first symbol type having a level transition in the corresponding symbol interval and (ii) represents a second bit value by a second symbol type having a constant level in the corresponding symbol interval. The processor is configured to derive an error signal from the digital samples, and to produce a quality measure of the received signal based on the derived error signal.

A receiver includes an interface and a processor. The interface is configured to receive a signal including symbols carrying bit values in respective symbol intervals, and to convert the received signal into a serial sequence of digital samples, the received signal being modulated using a Differential Manchester Encoding (DME) scheme that (i) represents a first bit value by a first symbol type having a level transition in the corresponding symbol interval and (ii) represents a second bit value by a second symbol type having a constant level in the corresponding symbol interval. The processor is configured to derive an error signal from the digital samples, and to produce a quality measure of the received signal based on the derived error signal.